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Jia3Xu's avatar
Jia3Xu
Icon for New Contributor rankNew Contributor
3 years ago

HLS generate testbench failed.

I wrote a kernel defines like this: void simulateDDR_512(mm_8bit_t& storage, ihc::stream_in<mmCmd>& txWriteCmdFifo, ihc::stream_out<mmStatus>& txWriteStatusFifo, ihc::stream_in<mmCmd>& txReadCmdFi...
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BoonBengT_Altera's avatar
BoonBengT_Altera
Icon for Moderator rankModerator
3 years ago

Hi @Jia3Xu,


Thank you for posting in Intel community forum and hope all is well.

For simulation verification on the IP there are certain prerequisite to check such as the version of questa and etc.

You may refer to the user guide below:

- https://www.intel.com/content/www/us/en/docs/programmable/683456/23-2/verifying-your-ip-with-simulation.html


May I asked which version and edition of HLS are you compiling with?

Note: the Intel HLS standard edition are supporting only modelsim as per my understanding.


Best Wishes

BB