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HLS generate testbench failed.
I wrote a kernel defines like this: void simulateDDR_512(mm_8bit_t& storage, ihc::stream_in<mmCmd>& txWriteCmdFifo, ihc::stream_out<mmStatus>& txWriteStatusFifo, ihc::stream_in<mmCmd>& txReadCmdFifo, ihc::stream_in<net_axis<DATA_WIDTH> >& txBufferIn, ihc::stream_out<net_axis<DATA_WIDTH> >& txBufferOut, ihc::stream_in<mmCmd>& rxWriteCmdFifo, ihc::stream_out<mmStatus>& rxWriteStatusFifo, ihc::stream_in<mmCmd>& rxReadCmdFifo, ihc::stream_in<net_axis<DATA_WIDTH> >& rxBufferIn, ihc::stream_out<net_axis<DATA_WIDTH> >& rxBufferOut); and the net_axis is defined as : template <int D> struct net_axis { ac_int<D, false> data; ac_int<D/8, false> keep; ac_int<1, false> last; net_axis() {} net_axis(ac_int<D, false> data, ac_int<D/8, false> keep, ac_int<1, false> last) :data(data), keep(keep), last(last) {} }; the emulation on x86-64 success. but simulation with questasim failed with Error: Creating x86-64 testbench Compiler Error: Cannot generate a testbench for component _Z15simulateDDR_512RN3ihc7mm_hostI6ac_intILi8ELb0EEJNS_6dwidthILi8EEENS_6awidthILi64EEENS_6aspaceILi1EEENS_7latencyILi0EEENS_8maxburstILi8EEENS_11waitrequestILi1EEEEEERNS_9stream_inI5mmCmdJEEERNS_10stream_outI8mmStatusJEEESK_RNSH_I8net_axisILi512EEJEEERNSL_ISQ_JEEESK_SO_SK_SS_SU_ because argument txBuffer is a pointer or reference to an opaque type. This may occur for templated types if the argument is unused in the component. HLS Testbench component wrapper generation FAILED. Makefile:27: recipe for target 'simulateDDR_512-sim' failed any ideas or solutions to this problem?2.1KViews0likes8CommentsRe: oneAPI FPGA use RTL module with avalon ST
hi harresh, This problem is basically from the website you provided. as illustrated in the document, I need to execute the following command fpga_crossgen lib_rtl_spec.xml --emulation_model lib_rtl_model.cpp --source sycl --target sycl -o lib_rtl.o and the error above occurs. could you please find some more information ? thanks a lot. B.R jia2.3KViews0likes0CommentsRe: using HLS generated code with oneAPI in fpga
Hi Boonbeng, Sorry for the late reply, Yes I've read the document, I've tried to compile that into an RTL way (which is synthsis the HLS code to an RTL module and use the rtl module and a c-sim function as the input of the fpga_crossgen, but because the HLS code is quite complicated which includes many streams_in /stream_out(avalon ST) interface, so I failed to manage complete the crossgen successfully according to the document you mentioned . But the document also mention the input arguments and the usage of fpga_corssgen( by invoke fpga_crossgen --help) also indicate that I can input a .cpp file and choose hls as the source (--source hls) and select target as sycl (--target sycl) to generate an object file suitable for sycl. fpga_crossgen ./compute_kernel.cpp --source hls --target sycl -o compute_kernel.o and that cause the problem in my first post. is that a valid operation? if ture, then comes to the int128 problem. I tried to solve the int128 problem but not work. here are my attempts. the website you mentioned , the url provided by jimdempseyatthecove is not able to access. I've tried the http://mx-3.cz/tringi/www/int128 class but the class is used not for oneAPI or hls kernel because of the usage of "throw" etc. is not allowed. I guess the problem may be some library include problem becasue when I use ipcx to compile the code with -fhls flag it exit with out error. (but this seems not able to make the hls code interact with the oneAPI kernel). Best Regards, Jia1.8KViews0likes0Commentsusing HLS generated code with oneAPI in fpga
Hi, I am developing a fpga project using oneAPI, and I want to use the code which is written by intel HLS. (Migrating to oneAPI is the least thing I want to do becasue the code in HLS is huge) so I use fpga_crossgen to compile the hls code to a library. and it generate a lot lines of error: In file included from /home/myname/workspace/fpga/toe/arp_intel/toe/toe.cpp:29: In file included from /home/myname/workspace/fpga/toe/arp_intel/toe/toe.hpp:31: In file included from /home/myname/workspace/fpga/toe/arp_intel/toe/../axi_utils.hpp:33: In file included from /usr/lib/gcc/x86_64-linux-gnu/12/../../../../include/c++/12/iostream:39: In file included from /usr/lib/gcc/x86_64-linux-gnu/12/../../../../include/c++/12/ostream:38: In file included from /usr/lib/gcc/x86_64-linux-gnu/12/../../../../include/c++/12/ios:42: In file included from /usr/lib/gcc/x86_64-linux-gnu/12/../../../../include/c++/12/bits/ios_base.h:41: In file included from /usr/lib/gcc/x86_64-linux-gnu/12/../../../../include/c++/12/bits/locale_classes.h:40: In file included from /usr/lib/gcc/x86_64-linux-gnu/12/../../../../include/c++/12/string:49: /usr/lib/gcc/x86_64-linux-gnu/12/../../../../include/c++/12/ext/numeric_traits.h:130:58: error: __int128 is not supported on this target __extension__ template<> struct __is_integer_nonstrict<__int128> { enum { __value = 1 }; typedef std::__true_type __type; enum { __width = 128 }; }; __extension__ template<> struct __is_integer_nonstrict<unsigned __int128> { enum { __value = 1 }; typedef std::__true_type __type; enum { __width = 128 }; }; ^ /usr/lib/gcc/x86_64-linux-gnu/12/../../../../include/c++/12/ext/numeric_traits.h:130:216: error: __int128 is not supported on this target __extension__ template<> struct __is_integer_nonstrict<__int128> { enum { __value = 1 }; typedef std::__true_type __type; enum { __width = 128 }; }; __extension__ template<> struct __is_integer_nonstrict<unsigned __int128> { enum { __value = 1 }; typedef std::__true_type __type; enum { __width = 128 }; }; ^ In file included from /home/myname/workspace/fpga/toe/arp_intel/toe/toe.cpp:29: In file included from /home/myname/workspace/fpga/toe/arp_intel/toe/toe.hpp:31: In file included from /home/myname/workspace/fpga/toe/arp_intel/toe/../axi_utils.hpp:41: In file included from /media/myname/oneapi/2023.2.0/compiler/2023.2.0/linux/lib/oclfpga/include/HLS/ac_int.h:112: In file included from /media/myname/oneapi/2023.2.0/compiler/2023.2.0/linux/lib/oclfpga/include/HLS/math.h:108: In file included from /usr/lib/gcc/x86_64-linux-gnu/12/../../../../include/c++/12/math.h:36: In file included from /usr/lib/gcc/x86_64-linux-gnu/12/../../../../include/c++/12/cmath:1935: In file included from /usr/lib/gcc/x86_64-linux-gnu/12/../../../../include/c++/12/bits/specfun.h:46: /usr/lib/gcc/x86_64-linux-gnu/12/../../../../include/c++/12/limits:1658:50: error: __int128 is not supported on this target __extension__ template<> struct numeric_limits<__int128> { static constexpr bool is_specialized = true; static constexpr __int128 min() noexcept { return (((__int128)(-1) < 0) ? -(((__int128)(-1) < 0) ? (((((__int128)1 << ((128 - ((__int128)(-1) < 0)) - 1)) - 1) << 1) + 1) : ~(__int128)0) - 1 : (__int128)0); } static constexpr __int128 max() noexcept { return (((__int128)(-1) < 0) ? (((((__int128)1 << ((128 - ((__int128)(-1) < 0)) - 1)) - 1) << 1) + 1) : ~(__int128)0); } static constexpr int digits = 128 - 1; static constexpr int digits10 = (128 - 1) * 643L / 2136; static constexpr bool is_signed = true; static constexpr bool is_integer = true; static constexpr bool is_exact = true; static constexpr int radix = 2; static constexpr __int128 epsilon() noexcept { return 0; } static constexpr __int128 round_error() noexcept { return 0; } static constexpr __int128 lowest() noexcept { return min(); } static constexpr int max_digits10 = 0; static constexpr int min_exponent = 0; static constexpr int min_exponent10 = 0; static constexpr int max_exponent = 0; static constexpr int max_exponent10 = 0; static constexpr bool has_infinity = false; static constexpr bool has_quiet_NaN = false; static constexpr bool has_signaling_NaN = false; static constexpr float_denorm_style has_denorm = denorm_absent; static constexpr bool has_denorm_loss = false; static constexpr __int128 infinity() noexcept { return static_cast<__int128>(0); } static constexpr __int128 quiet_NaN() noexcept { return static_cast<__int128>(0); } static constexpr __int128 signaling_NaN() noexcept { return static_cast<__int128>(0); } static constexpr __int128 denorm_min() noexcept { return static_cast<__int128>(0); } static constexpr bool is_iec559 = false; static constexpr bool is_bounded = true; static constexpr bool is_modulo = false; static constexpr bool traps = true; static constexpr bool tinyness_before = false; static constexpr float_round_style round_style = round_toward_zero; }; __extension__ template<> struct numeric_limits<unsigned __int128> { static constexpr bool is_specialized = true; static constexpr unsigned __int128 min() noexcept { return 0; } static constexpr unsigned __int128 max() noexcept { return (((unsigned __int128)(-1) < 0) ? (((((unsigned __int128)1 << ((128 - ((unsigned __int128)(-1) < 0)) - 1)) - 1) << 1) + 1) : ~(unsigned __int128)0); } static constexpr unsigned __int128 lowest() noexcept { return min(); } static constexpr int max_digits10 = 0; static constexpr int digits = 128; static constexpr int digits10 = 128 * 643L / 2136; static constexpr bool is_signed = false; static constexpr bool is_integer = true; static constexpr bool is_exact = true; static constexpr int radix = 2; static constexpr unsigned __int128 epsilon() noexcept { return 0; } static constexpr unsigned __int128 round_error() noexcept { return 0; } static constexpr int min_exponent = 0; static constexpr int min_exponent10 = 0; static constexpr int max_exponent = 0; static constexpr int max_exponent10 = 0; static constexpr bool has_infinity = false; static constexpr bool has_quiet_NaN = false; static constexpr bool has_signaling_NaN = false; static constexpr float_denorm_style has_denorm = denorm_absent; static constexpr bool has_denorm_loss = false; static constexpr unsigned __int128 infinity() noexcept { return static_cast<unsigned __int128>(0); } static constexpr unsigned __int128 quiet_NaN() noexcept { return static_cast<unsigned __int128>(0); } static constexpr unsigned __int128 signaling_NaN() noexcept { return static_cast<unsigned __int128>(0); } static constexpr unsigned __int128 denorm_min() noexcept { return static_cast<unsigned __int128>(0); } static constexpr bool is_iec559 = false; static constexpr bool is_bounded = true; static constexpr bool is_modulo = true; static constexpr bool traps = true; static constexpr bool tinyness_before = false; static constexpr float_round_style round_style = round_toward_zero; }; 44 errors generated. Error: OpenCL parser FAILED seems the error occurs when include ac_int.h which is necessary for the code to use. any ideas on this problem? B.R.&thanks Jia1.9KViews0likes6CommentsRe: oneAPI FPGA use RTL module with avalon ST
Hi hareesh, I've watched that video, but I think the problem still exists. 1. the video is about OpenCL, not oneAPI, they are the same in most part, but some slightly different in some way like compiling etc. 2. the video is mostly the same as the document and of the oneAPI https://www.intel.com/content/www/us/en/docs/oneapi/programming-guide/2023-1/use-of-rtl-libraries-for-fpga.html and I've tried that, and also tried the corresponding sample provided in https://github.com/oneapi-src/oneAPI-samples/blob/master/DirectProgramming/C%2B%2BSYCL_FPGA/Tutorials/Tools/use_library/README.md but both of them doesn't mention about how to implement an RTL module with multiple avalonST interfaces as an oneAPI library. I did some attempt but it doesn't work. the problem I stcuk is in the fpga_crossgen. the verilog declaration of my module is like this: ip_handler_top ip_handler_top_inst ( // Interface: clock (clock end) .clock ( ), // 1-bit clk input // Interface: reset (reset end) .resetn ( ), // 1-bit reset_n input // Interface: s_axis_raw (avalon_streaming sink) .s_axis_raw_data ( ), // 640-bit data input .s_axis_raw_ready ( ), // 1-bit ready output .s_axis_raw_valid ( ), // 1-bit valid input // Interface: m_axis_arp (avalon_streaming source) .m_axis_arp_data ( ), // 640-bit data output .m_axis_arp_ready ( ), // 1-bit ready input .m_axis_arp_valid ( ), // 1-bit valid output // Interface: call (conduit sink) .start ( ), // 1-bit valid input .busy ( ), // 1-bit stall output // Interface: return (conduit source) .done ( ), // 1-bit valid output .stall ( ), // 1-bit stall input // Interface: myIpAddress (conduit sink) .myIpAddress ( ) // 32-bit data input ); first time I tried to set the avalone interface as input in the xml file:(snippet below) <INPUT port="s_axis_raw_data" width="640" /> <OUTPUT port="s_axis_raw_ready" width="1" /> <INPUT port="s_axis_raw_valid" width="1" /> <OUTPUT port="m_axis_arp_data" width="640" /> <INPUT port="m_axis_arp_ready" width="1" /> <OUTPUT port="m_axis_arp_valid" width="1" /> <OUTPUT port="m_axis_icmp_data" width="640" /> it return error says Errors in HDL component specification file:Error in './ip_handler_ip.xml', line 21 Expected element <OUTPUT> to appear exactly once. and if change the type to avalon, seems no luck to me. is there any possible way to do this, that is to use a RTL module with avalonST interface as a oneAPI library?2.5KViews0likes0Comments