oneAPI FPGA use RTL module with avalon ST

Hi hareesh,

I've watched that video, but I think the problem still exists.

1. the video is about OpenCL, not oneAPI, they are the same in most part, but some slightly different in some way like compiling etc.

2. the video is mostly the same as the document and of the oneAPI https://www.intel.com/content/www/us/en/docs/oneapi/programming-guide/2023-1/use-of-rtl-libraries-for-fpga.html and I've tried that, and also tried the corresponding sample provided in https://github.com/oneapi-src/oneAPI-samples/blob/master/DirectProgramming/C%2B%2BSYCL_FPGA/Tutorials/Tools/use_library/README.md
but both of them doesn't mention about how to implement an RTL module with multiple avalonST interfaces as an oneAPI library.

I did some attempt but it doesn't work.

the problem I stcuk is in the fpga_crossgen.
the verilog declaration of my module is like this:

ip_handler_top ip_handler_top_inst (
// Interface: clock (clock end)
.clock ( ), // 1-bit clk input
// Interface: reset (reset end)
.resetn ( ), // 1-bit reset_n input
// Interface: s_axis_raw (avalon_streaming sink)
.s_axis_raw_data ( ), // 640-bit data input
.s_axis_raw_ready ( ), // 1-bit ready output
.s_axis_raw_valid ( ), // 1-bit valid input
// Interface: m_axis_arp (avalon_streaming source)
.m_axis_arp_data ( ), // 640-bit data output
.m_axis_arp_ready ( ), // 1-bit ready input
.m_axis_arp_valid ( ), // 1-bit valid output
// Interface: call (conduit sink)
.start ( ), // 1-bit valid input
.busy ( ), // 1-bit stall output
// Interface: return (conduit source)
.done ( ), // 1-bit valid output
.stall ( ), // 1-bit stall input
// Interface: myIpAddress (conduit sink)
.myIpAddress ( ) // 32-bit data input
);

first time I tried to set the avalone interface as input in the xml file:(snippet below)

      <INPUT port="s_axis_raw_data"  width="640" />
      <OUTPUT port="s_axis_raw_ready"  width="1" />
      <INPUT port="s_axis_raw_valid"  width="1" />
      <OUTPUT port="m_axis_arp_data"  width="640" />
      <INPUT port="m_axis_arp_ready"  width="1" />
      <OUTPUT port="m_axis_arp_valid"  width="1" />
      <OUTPUT port="m_axis_icmp_data"  width="640" />

Errors in HDL component specification file:Error in './ip_handler_ip.xml', line 21
Expected element <OUTPUT> to appear exactly once.

and if change the type to avalon, seems no luck to me.

is there any possible way to do this, that is to use a RTL module with avalonST interface as a oneAPI library?