Forum Discussion
ContributorError (23035) Tcl error running dla_build_example_design.py script
Hello,
I got this error when I run "dla_build_example_design.py" esample script with Intel FPGA AI suite. It is run according to the "Intel FPGA AI Suite SoC Design Example User Guide" and it should be executed even the license was not valid. According to documentation if the ir no license available, bitstreams should be compiled but with limited inferences. However, I am not able to compile it.
"
nfo: Command: quartus_cpf -c --hps -o bitstream_compression=on output_files/top.sof output_files/top.rbf
Error (213009): File name "output_files/top.sof" does not exist or can't be read
Error: Quartus Prime Convert_programming_file was unsuccessful. 1 error, 0 warnings
Error: Peak virtual memory: 721 megabytes
Error: Processing ended: Mon Sep 11 12:38:19 2023
Error: Elapsed time: 00:00:00
Error: System process ID: 517860
Error (23035): Tcl error: ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last.
while executing
"execute_module -tool cpf -args "-c --hps -o bitstream_compression=on output_files/top.sof output_files/top.rbf""
(file "generate_sof.tcl" line 5)
------------------------------------------------
ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last.
while executing
"execute_module -tool cpf -args "-c --hps -o bitstream_compression=on output_files/top.sof output_files/top.rbf""
(file "generate_sof.tcl" line 5)
------------------------------------------------
Error (23031): Evaluation of Tcl script generate_sof.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 8 errors, 745 warnings
Error: Peak virtual memory: 1037 megabytes
Error: Processing ended: Mon Sep 11 12:38:19 2023
Error: Elapsed time: 00:21:00
Error: System process ID: 513901
Error: A license needed by one or more of the IP components in the design was not found. Contact Intel if you wish to obtain a license for the Intel FPGA AI Suite.
Command Failed quartus_sh -t generate_sof.tcl
"
--
OpenVino version: 2022.3
Intel FPGA AI Suite version: 2023.2
Device: Intel Arria 10 SoC FPGA
OS: Ubuntu 20.04
31 Replies
JohnT_AlteraRegular Contributor
Hi,
Can you provide the full Quartus compilation report? May I know if you have Quartus license?
RubenPadialHello @JohnT_Intel,
Yes, I have a Quartus license. Could you tell me where it is saved Quartus compilation report by default?
- JohnT_Altera
Hi,
It should be in "dla\<build dir>\hw\output_files"
Thanks
- RubenPadial
Hello @JohnT_Intel
Here you are. I edited the files so as not to spread license information.
- JohnT_Altera
Hi,
From the report, it looks like you do not have Nios V IP license.
You can check on asm.rpt file.
Warning (115005): Unlicensed IP: "Nios V Soft Processor FPGA IP - M Core (6AF7 D036)"
- RubenPadial
Hello @JohnT_Intel ,
I've noticed the warning, but it's important to clarify that it's a warning and not an error. I haven't found any mention of the need for a Nios V license in the Intel FPGA AI Suite documentation. Specifically, neither the 'Intel FPGA AI Suite IP Reference Manual,' the 'Intel FPGA AI Suite SoC Design Example User Guide,' nor the 'Intel FPGA AI Suite: Getting Started Guide' states that a Nios V license is required. These documents mention the need for an Intel FPGA AI Suite license to compile the bitstream and Intel Quartus Pro, but not a Nios V license.
- JohnT_Altera
Hi,
The Nios V is needed when you are performing AI Suite with streaming method. Usually, Nios V will be part of the Quartus license.
Below is the warning related to the sof file not generated.
Warning (115003): Can't generate programming files for your current project because you do not have a valid license for the following IP core or cores.
- RubenPadial
Hi @JohnT_Intel,
Thank you for the clarification.
I got the Nios V-m license and I have another error while compiling. I am no able to find the rootcause. It seems a license error but I cannot find which one. Log files are attached to this mail. However, 4_A10_M2M profile was successfully compiled.
- JohnT_Altera
Hi,
It looks like theree is some issue with your license.
Beklow is the error which is still targetting Nios V License
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_unit_2141/synth/opcode_def.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_unit_2141/synth/alu.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_unit_2141/synth/instr_decoder.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_unit_2141/synth/lsu.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_unit_2141/synth/nios_top.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_unit_2141/synth/reg_file.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_unit_2141/synth/csr.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_unit_2141/synth/interrupt_handler.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_unit_2141/synth/shift_module.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_unit_2141/synth/mult_module.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_unit_2141/synth/instr_prefetch.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_unit_2141/synth/instruction_buffer.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_timer_msip_110/synth/timer_msip.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_dbg_mod_110/synth/dm_def.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_dbg_mod_110/synth/dm_jtag2mm.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_dbg_mod_110/synth/dm_top.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_dbg_mod_110/synth/debug_module.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_dbg_mod_110/synth/debug_rom.sv'
- RubenPadial
Hello @JohnT_Intel
Thank you for your support. The message shows some issue with license but the message is not clear. I have the Intel® FPGA IP IP-NIOSVM license. Is there any other license needed?
Could you remove the confidential license information you shared in the previous message?
- JohnT_Altera
Hi,
- 6AF7_D036 License issue.
- Please check if the file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_unit_2141/synth/opcode_def.sv' is generated? It looks like missing from your design.
- RubenPadial
Hello @JohnT_Intel,
- 6AF7_D036 License issue. --> Is that the "Intel® FPGA IP IP-NIOSVM" license?
- Please check if the file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_unit_2141/synth/opcode_def.sv' is generated? It looks like missing from your design. --> Yes, that file was generated like the other files reported in the error messages. Find "intel_niosv_m_unit_2141.zip" file attached to this message. "My design" is the SoC Design Example. I'm only trying to reproduce it.
- JohnT_Altera
Hi,
You can check your Quartus license for this ID. I am not seeing this ID in my Quartus license.
I do not observed any attachment
- RubenPadial
Hello @JohnT_Intel
Sorry, now intel_niosv_m_unit_2141.zip file is attached.
Find below and screenshot of the NIOS V license status in quartus license manager.
- JohnT_Altera
Hi,
The file is just qsys generateed file. May I know what is the step that I can performed to duplicate your issue?
Or how do you add the AI Suite design into your project?
- RubenPadial
Hello @JohnT_Intel
I'm currently assesing Intel FPGA AI suite use in my project. You can reproduce the issue executing SoC Design example "3.3.2. Building the FPGA Bitstreams":
"
dla_build_example_design.py \
-ed 4_A10_S2M \
-n 1 \
-a \
$COREDLA_ROOT/example_architectures/A10_Performance.arch \
--build \
--build-dir \
$COREDLA_WORK/a10_perf_bitstream \
--output-dir $COREDLA_WORK/a10_perf_bitstream"
- JohnT_Altera
Hi,
It looks like there might be some issue with your license which cause it not able to compile the design..
Below is the output if you have the license.
- RubenPadial
Hello @JohnT_Intel,
That's the initial question. I realized there's a licensing error after activating the Nios V license, but I'm unable to pinpoint the root cause. Is there any other license required?
We seem to be stuck at the same point after exchanging 11 messages. I realy appreciate your support, but it would be very helpful if we could schedule a meeting or discuss this via email. Is that possible?
