Forum Discussion
Hi,
It looks like theree is some issue with your license.
Beklow is the error which is still targetting Nios V License
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_unit_2141/synth/opcode_def.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_unit_2141/synth/alu.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_unit_2141/synth/instr_decoder.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_unit_2141/synth/lsu.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_unit_2141/synth/nios_top.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_unit_2141/synth/reg_file.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_unit_2141/synth/csr.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_unit_2141/synth/interrupt_handler.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_unit_2141/synth/shift_module.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_unit_2141/synth/mult_module.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_unit_2141/synth/instr_prefetch.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_unit_2141/synth/instruction_buffer.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_timer_msip_110/synth/timer_msip.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_dbg_mod_110/synth/dm_def.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_dbg_mod_110/synth/dm_jtag2mm.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_dbg_mod_110/synth/dm_top.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_dbg_mod_110/synth/debug_module.sv'
Warning (292000): FLEXlm software error: Bad message command. Feature: 6AF7_D036 License
Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'qsys/ip/dla/dla_niosv_0/intel_niosv_m_dbg_mod_110/synth/debug_rom.sv'
- RubenPadial3 years ago
Contributor
Hello @JohnT_Intel
Thank you for your support. The message shows some issue with license but the message is not clear. I have the Intel® FPGA IP IP-NIOSVM license. Is there any other license needed?
Could you remove the confidential license information you shared in the previous message?