Forum Discussion
JohnT_Altera
Regular Contributor
3 years agoHi,
The file is just qsys generateed file. May I know what is the step that I can performed to duplicate your issue?
Or how do you add the AI Suite design into your project?
RubenPadial
Contributor
3 years agoHello @JohnT_Intel
I'm currently assesing Intel FPGA AI suite use in my project. You can reproduce the issue executing SoC Design example "3.3.2. Building the FPGA Bitstreams":
"
dla_build_example_design.py \
-ed 4_A10_S2M \
-n 1 \
-a \
$COREDLA_ROOT/example_architectures/A10_Performance.arch \
--build \
--build-dir \
$COREDLA_WORK/a10_perf_bitstream \
--output-dir $COREDLA_WORK/a10_perf_bitstream
"