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hls_flow_questioner's avatar
hls_flow_questioner
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1 year ago

Accessing global memory with HLS flow authoring oneAPI kernel

Hello, I was wondering how one goes about configuring a oneAPI kernel to be able to access either off-chip DDR memory or on-chip esRAM when plugging the design into Platform Designer after compilati...
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BoonBengT_Altera's avatar
BoonBengT_Altera
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1 year ago

Hi @hls_flow_questioner,


Thank you for posting in Intel community forum, hope all is well and apologies for the delayed in response.

There are several ways to access the memory from kernel as below:

- https://www.intel.com/content/www/us/en/docs/oneapi-fpga-add-on/optimization-guide/2023-1/memory-accesses.html


In addition you can followed the optimization guide to use caching as well:

- https://www.intel.com/content/www/us/en/docs/oneapi-fpga-add-on/optimization-guide/2023-1/improve-loop-performance-by-caching-on-chip-memory.html


And yes an communication interface would be required for those IP to communication and usually it would be the Avalon interface.

May I know what device that you are working with and also the oneAPI version that you are looking for?

Hope that clarify


Best Wishes

BB