Which tDQSS timing parameter should be used in the UniPHY LPDDR2 IP Memory Timing tab of the parameter editor?
3 years ago76Views0likes0CommentsHow do I connect the detected_rate and detected_rate_in signals from the Serial Digital Interface (SDI) MegaCore?
4 years ago56Views0likes0CommentsAre there any known issues when selecting an Input REFCLK frequency in the Low Latency PHY for a Stratix® V GT FPGA channel?
3 years ago77Views0likes0CommentsWhy do I get minimum period timing violation in UniPHY-based DDR3 SDRAM Controller on a Stratix® V device?
3 years ago78Views0likes0Comments- 4 years ago109Views0likes0Comments
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