Are there any known issues when selecting an Input REFCLK frequency in the Low Latency PHY for a Stratix® V GT FPGA channel?

Description

Yes, due to a bug in the Low Latency PHY parameter editor, you can select illegal REFCLK frequencies for Stratix® V GT devices. Valid REFCLK frequencies are based on a data rate divider ratio of 16 or 20 and should also consider the F(max) of the device REFCLK pin.

For example, a 25 Gbps data rate would result in either a 781.25 MHz or 625 MHz REFCLK. As the Fin(max) of the REFCLK pin is 717 MHz, the only valid REFCLK frequency would be 625 MHz.

Resolution

This problem has been fixed in the Quartus® II software version 13.0.