Most RecentHow do I select which hard memory controller to use if my FPGA has two controllers?Unable to generate MSI interruptOn-chip memory initialization after partial reconfiguration (arria 10)JESD204B Rx Phase Compensation FIFO fullI was built a new quartus project that include both 10g MAC and 10gbase-r phy,the output interface pll_ref_clk of PHY need a 322.265625MHz clock,but PIN_AK7 is a 100MHz clock,how can this clock satisfy the PHY's need?Since Quartus II 18.1.1: floating license does not work anymore.How to use PLL Locked outputusage of SGDMA IP for data transfer to and from DDR3Multiple Quartus versions installed 6.0 to 12.1 SP1, Win 7 IP Megastore used to work. Now nothing in any version. - did installation of newer Quartus versions make this stop working? or - because my subscription licence is now past expired?I need a current RoHS and REACH Declaration of Conformity for Intel part number 10M50DAF256i7G. Can someone please provide these. We have to have them before we can use this part.
