Hie,
My apologies for the delayed first response. I got your case mixed up with another PCIe forum question; hence I missed providing an update.
Basically to enable MSI interrupt in the FPGA, you need to set the MSI Enable bit and disable the Legacy Interrupt bit in Configuration Space registers.
Hence, the MSI interrupt is enabled correctly for the FPGA in steps 1 till 3 if used as EP or RP.
The RP or EP could have different flow to enable MSI interrupt depending on the type of device used.
For MSI interrupt handling for FPGA devices, you can refer to the following link for more details on the MSI interrupt generation and handling flow.
https://fpgawiki.intel.com/wiki/Handling_PCIe_Interrupts#Enable_MSI
For now, I cannot find anything wrong with your steps. I will need more information such as following to understand the failure you are facing.
i. EP and RP used ; are both using FPGA. If yes, which device
ii. PCIe interface used; AVMM, AVST or others
iii. Signal tap all Avalon ST (both Tx and Rx signals) or txs interface signals if using AVMM:
Ex: tx_st_data, tx_st_eop, tx_st_sop, tx_st_empty, tx_st_ready, tx_st_valid, tx_st_err, tx_st_parity, rx_st_data, rx_st_eop, rx_st_sop, rx_st_empty, rx_st_ready, rx_st_valid, rx_st_err,
iv. The MSI handling flow in your system
As for checking MSI interrupt generation, you could either use a protocol analyzer to determine the type of TLP or check the Avalon ST interface or txs in signaltap.
Please let me know if you understood my reply and have further questions.
Regards,
Nathan
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