Most Recent2Gb setting with PFLwhat is the option to initiate the DDR3L calibration? how long it will take to complete the calibration?do the LPM_SHIFTREG must be used in the spi serial receiving code when the clock fequency is too fast?XXX. Sof was downloaded to FPGA, Contains a 5G LDPC IP,i find the signal (sink_ready) always low,why rx_is_lockedtodata is not set to 1 after the work of the controller?I am trying to create a Viterbi IP block and use in my Arria V GZ design. I am not running an Avalon bus internal. I see that when I choose the Viterbi IP from the DSP/Error Detection and Correction section, it is generated using Qsys.Where can i get Quartus Programmer software v14 for 32 Bit?I have downloaded HDLC IP from opencores which is having front side bus as wishbone, I am using CYCLONE 4 FPGA with NIOS II processor. I want to interface HDLC IP to NIOS processor(AVALON BUS) please explain how to interface.is there any option to change the data width of Avalon interface in ddr3 controller?PFL Devices Support
