Most RecentClock source IP is not generating the frequency provided in "clock frequency" parameter of the IP.in the document: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-altlvds-14.1.pdf, page 18error 14996 & 175001 of fitter placement in Quartus 18.1 proPLL_50_100 usage: Simulation refers to wrong path of altera_mf.v and simulation hangs.Error 14566 when using the PCIe Hard IP Core next to the Custom Transceiver IP Core on a Cyclone V GXNIOS : fopen command only works if using the NIOSII Debug toolTriple-Speed Ethernet MegaCore Function user guide, ug_ethernet.pdf, figure 8.1 shows ff_tx_clk and ff_rx_clk at 110 MHz, but table 8.1 lists a recommended frequency of 100 MHz, which is right?No fpga detection by doing lspciSDI II IP - TX sync IssueBit Slip logic implementation for Stratix 10 Native PHY with PCS Direct mode
