Occasional ContributorI added new FPGA arria 10 to my pcie slot, and after doing installation as mentioned I did lspci it not able to detect , but with lsusb it gives the device attached. Can any help me with the issue, ?
ContributorPlease explain your power up procedure - specifically how and when the FPGA is being programmed. In order for a device to appear in the PCIe space it must be available for arbitration (be programmed) within 100ms of power up...
Refer to the 'PCIe* Timing Sequence in CvP Initialization Mode'
https://www.intel.com/content/www/us/en/programmable/documentation/spz1472766124531.html#uok1491597976510
What hardware are you using? A development board or something custom?
Cheers,
Alex
Regular ContributorHi,
Do you able to see the device if you restart the PC and does the configuration completed? What board that you are actually using?
Regards -SK
Occasional ContributorHi ,
I am using Arria 10 FPGA GX development board. I have done that still no luck, I have installed in a way how user guide suggests it is still not working. When I do quartu_pgm -l , I am able to see the it detects Jtag connected to it but still after doing all the steps , Fpga is not being detected
Regular ContributorThere are a few PCIe example designs for the Arria 10 FPGA GX development board. For example AN456 (link below) or you can generate the example from the PCIe IP GUI as well.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an456.pdf
Could you please try to use these examples? Or Change to use other PCIe slot or another host? This is just to determine if there is any dependency.
To further debug, it is required to capture the signals like ltssmstate, current_speed and lane_act by using signaltap to investigate.
Regards -SK
Occasional ContributorHi @SengKokL_Intel PCIe IP GUI is only for windows version. Is there any support available for linux OS preferably red hat OS available ?
Regular ContributorWhat I mean is, you can instantiate the PCIe IP from Quartus's IP catalog, or Platform designer, from the GUI there, you can configure the IP and then generate the PCIe example design. This is regardless to the OS. Or you can use the design from AN456.
New ContributorWhat I mean is, you can instantiate the PCIe IP from Quartus' IP index, or Stage originator, from the GUI there, you can arrange the IP and after that produce the PCIe model structure. This is in any case to the operating system. Or then again you can utilize the plan from AN456.
