Occasional ContributorError 14566 when using the PCIe Hard IP Core next to the Custom Transceiver IP Core on a Cyclone V GX
The device is the 5CGXFC9C7F23C8 and the Quartus version 17.1 is used.
The Avalon-MM CV Hard IP for PCIe is configured as Gen1 x4.
The Custom PHY component has one lane in Duplex mode enabled. (The goal is to use two lanes in Duplex mode)
The two IP Cores share one Reconfiguration Controller.
The analysis & synthesis is running without any errors but the fitter gives me following error message:
Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 Channel PLL(s)).
Looking in the Resource Usage Summary of the a&s this makes sense, because it shows that 7 Channel PLLs are being used. When trying without the Custom PHY it shows that 5 Channel PLLs are used. (The device has 6).
As far as I understand, the PCIe Core uses 5 becuase of: "one for the TX PLL and one for the channels" (from this document ).
Why is that? The figures 7-37 and 7-38 in the document above make it seem as if one additional channel PLL (1 or 4) was used for clock generation (TX PLL) for the other transceiver channels and their local PLLs. Is that correct?
Further reading revealed that the Custom PHY Core has the same needs in regard of PLLs.
My conclusion to this is, that I need a FPGA that has more Transceiver channels available (at least 8, so probably one that has 9)
Is this correct or is there any other way to implement even one of the two Duplex lanes of the Custom PHY Core? Is it possible to somehow share some resources or place the TX PLL "inside" the FPGA (for slower interfaces) ?
As you have probably mentioned I am pretty new to using Intel FPGAs transceiver interfaces, but I am doing my best trying to understand them.
- Hie, My apologies for the delayed first reply to your forum questions. I had another transceiver IP question and mistaken that I have answered the following question. Basically, the device 5CGXFC9C7F23C8 used has 6 transceiver channels. As you have used PCIe Gen1x4; it means you are using up 5 transceiver channels. For Cyclone V, we only offer fPLL and CMU PLL as transmitter PLL. CMU PLL uses up one transceiver channel resource. fPLL does not sacrifice any transceiver channels. For PCIe, it is a requirement to use CMU PLL as the fPLL cannot meet the jitter requirements. Hence, to enable PCIe Gen1x4, you will use up 5 transceiver channels. Please check my replies to your questions: Question: Why is that? The figures 7-37 and 7-38 in the document above make it seem as if one additional channel PLL (1 or 4) was used for clock generation (TX PLL) for the other transceiver channels and their local PLLs. Is that correct? Response: Yes, you are correct. Channel PLL 1 or 4 is used for clock generation. Question: My conclusion to this is, that I need a FPGA that has more Transceiver channels available (at least 8, so probably one that has 9) Is this correct or is there any other way to implement even one of the two Duplex lanes of the Custom PHY Core? Is it possible to somehow share some resources or place the TX PLL "inside" the FPGA (for slower interfaces) ? Response: Yes, you are correct. To implement PCIe Gen1x4 and two Duplex lanes of the custom phy core, you will need at least 7 channels. The duplex channels can use the fPLL as transmitter PLL which does not sacrifice one transceiver channel. fPLL has higher transmitter jitter and currently can support till 3.125Gbps. We do not have a 7 channels device, hence you will need to use a 9 channel device. I am afraid, there is no other option to enable PCIe without using 5 channels. However, if you only using one Duplex channel, you can still use the existing 6 transceiver channel device. Regards, Nathan
