Forum Discussion
FHint
Occasional Contributor
7 years agoError 14566 when using the PCIe Hard IP Core next to the Custom Transceiver IP Core on a Cyclone V GX
The device is the 5CGXFC9C7F23C8 and the Quartus version 17.1 is used. The Avalon-MM CV Hard IP for PCIe is configured as Gen1 x4. The Custom PHY component has one lane in Duplex mode enabled. (The...
- 7 years agoHie, My apologies for the delayed first reply to your forum questions. I had another transceiver IP question and mistaken that I have answered the following question. Basically, the device 5CGXFC9C7F23C8 used has 6 transceiver channels. As you have used PCIe Gen1x4; it means you are using up 5 transceiver channels. For Cyclone V, we only offer fPLL and CMU PLL as transmitter PLL. CMU PLL uses up one transceiver channel resource. fPLL does not sacrifice any transceiver channels. For PCIe, it is a requirement to use CMU PLL as the fPLL cannot meet the jitter requirements. Hence, to enable PCIe Gen1x4, you will use up 5 transceiver channels. Please check my replies to your questions: Question: Why is that? The figures 7-37 and 7-38 in the document above make it seem as if one additional channel PLL (1 or 4) was used for clock generation (TX PLL) for the other transceiver channels and their local PLLs. Is that correct? Response: Yes, you are correct. Channel PLL 1 or 4 is used for clock generation. Question: My conclusion to this is, that I need a FPGA that has more Transceiver channels available (at least 8, so probably one that has 9) Is this correct or is there any other way to implement even one of the two Duplex lanes of the Custom PHY Core? Is it possible to somehow share some resources or place the TX PLL "inside" the FPGA (for slower interfaces) ? Response: Yes, you are correct. To implement PCIe Gen1x4 and two Duplex lanes of the custom phy core, you will need at least 7 channels. The duplex channels can use the fPLL as transmitter PLL which does not sacrifice one transceiver channel. fPLL has higher transmitter jitter and currently can support till 3.125Gbps. We do not have a 7 channels device, hence you will need to use a 9 channel device. I am afraid, there is no other option to enable PCIe without using 5 channels. However, if you only using one Duplex channel, you can still use the existing 6 transceiver channel device. Regards, Nathan
FHint
Occasional Contributor
7 years agoHello again,
1) + 2) Thank you very much, that cleared a lot things up for me! Where does one find the information you provided? I feel like I went through the whole internet.
3) Do you know where I can read about the PLLs needed for PCIe Gen3 x8? Does this configuration need 9 Channel PLLs or 1 extra per 4 Lanes, which would sum up to 10?
4) Does the fPLL data rate (3.125 Gbps) you mentioned above also apply to the Arria 10 devices? Based on that information it should be possible to use it for 2125 Mbps links but not for interfaces like 10 GigE.
Best Regards,
Florian