Most RecentViterbi IP - BER estimate error numberHelp with A10 Backplane Auto NegotiationHow to setup Transceiver Phy Serial Loopback using C ApplicationHow to map the "DRDout" to GPIO of ufm in MAX VHow do I select which hard memory controller to use if my FPGA has two controllers?Unable to generate MSI interruptOn-chip memory initialization after partial reconfiguration (arria 10)JESD204B Rx Phase Compensation FIFO fullI was built a new quartus project that include both 10g MAC and 10gbase-r phy,the output interface pll_ref_clk of PHY need a 322.265625MHz clock,but PIN_AK7 is a 100MHz clock,how can this clock satisfy the PHY's need?Since Quartus II 18.1.1: floating license does not work anymore.
