Most RecentIs it allowed to connect two pll inclk0 to the same input clock ?The difference of ALt_pll/Altera pllFitter can't place ATX PLL on Stratix 10Cyclone5 development kit PCIE link fail.Modelsim error on altera_onchip_flash_block - Error: (vsim-3033): Instantiation of 'altera_onchip_flash_block' failed. The design unit was not found.question about lpm_divide pipeline ?platform designer display font is too smallhow can we get the hdl source code of platform design ipRemote update IP core problem。three sof：factory、app1、app2 。 Is Altera able to jump directly from app1 to app2?Can nPERST pins be used as PCIe reset if Intel® Stratix® 10 PCI Express* Hard IP is used as Root Complex?
