Most RecentCan the altera_pll version 18.0 be used on Cyclone V without the RREF_TL pin connected?About DP and HDMI IP，do they support 240HZ？such as 1080P@240hzDisplay Port Example ProjectHDMI RX IP questionHDMI compliance issueIn the Low Latency 100G Ethernet Intel®Stratix® 10 FPGA IP Core, can one of the two ATX PLLs be used as a clock buffer?Arria10 DMA失败Avalon -MM Intel Stratix 10 Hard IP+ for PCI ExpressWhat are some possible causes for EMIF IP for DDR4 Error "iossm_bf_cpu_cpu_test_bench/ihp_read is 'x'" during calibration for a non-HPS EMIF IP?I've instantiated a HDMI RX interface. it only can receive standard 1080P and 4K format. for a special 2K format(resolution 2560*1080), it cannot be parsed. Any different settings for this special resolution or it's just the feature?
