Most RecentDATA acquisition from unknown port of ASIC boardChip-to-Chip AXI for AlteraEP4CE30/40 missing F324 orcad schematic symbolsFPGA-to-HPS SDRAM vs. HPS-to-FPGACyclone III PLL loses lock at >75CmSGDMA stride reads/writesAssociating a VHDL RECORD with a bufferDDR3 Burst BL8 problemFlip-flop with aload?Stratix V CONF_DONE but no INIT_DONE
