Flip-flop with aload?

Hi everyone,

I recently wrote up an SPI send-and-receive module in SystemVerilog, and it's working nicely on an FPGA. Nevertheless, the synthesizer generated something slightly unexpected: a dedicated module for shifting data. (I've attached an image).

http://www.alteraforum.com/forum/attachment.php?attachmentid=9465&stc=1

I was intending to synthesize a row of flip-flops and muxes, but I instead got a more specific flip-flop with the following specs:

Inputs: D, CLK, DATA, ALOAD

Output: Q

Does anyone know the name of this particular flip flop or the internal logic that it's composed of?

It appears that this flip-flop does NOT trigger a transfer of the DATA signal on the edge but rather whenever the ALOAD signal is high.

Thanks!