Most RecentCyclone 10 GX Development Kit ddr problemCyclone 10 GX EMIF IP clockwe are using Arria 10 SoC FPGA Development Kit Board. generated example design and trying to do Ethernet test (PHY Serial loopback). we are getting CRC errorshow I can fix LABs requirements? I use the DE1_soc board, OS is ubuntu 18.04, and the intelFPGA_18.1 standard version. when I was trying to Compiling for FPGA then the following error generated.Why is the GTX clock output of the HPS running at 250 MHz?Chess digital clock with VHDL using FPGAFor the driver of a Modular Scatter-Gather DMA I need the header file "modular_sgdma_dispatcher.h". How can I get it, or what is the correct way to use "alt_msgdma_open" ?We need to replace an ACEX 1K FPGA model EP1K100. The suggested replacement for ACEX 1K is the MAX V; however, the MAX V only has 2210 LEs which isn't enough (EP1K100 has 4992 LEs). The MAX 10 is a better match. Is this an appropriate choice?How can I connect the UART pins on the DE10 nano to the USB mini-B connector?Linux for Arria5 build problem
