avib
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Re: eSPI to LPC bridge I/O transactions
Hi Thank you for your reply. It appears that there were missing assignments in our BIOS, and that the desired address ranges were not opened. Now that the BIOS was updated, we are able to perform I/O transactions using the eSPI to LPC IP. Thank you Avi1.9KViews0likes0CommentseSPI to LPC bridge I/O transactions
Hello, We are currently working on a new Intel SBC board that is based on legacy boards that utilized older Intel platforms like Coffee Lake. These legacy boards utilized an LPC bus to connect the PCH and FPGA device, with the PCH performing RD/WR operations from the FPGA registers through LPC I/O commands. However, our new board, which includes the MAX10 FPGA, is based on the Tiger Lake CPU, which no longer supports the LPC bus and instead uses the eSPI bus. In an attempt to bridge the PCH's eSPI and the FPGA's LPC interface, we tried adding Intel's eSPI to LPC bridge. Unfortunately, this process has proven to be more challenging than anticipated. We have opened the same LPC address ranges as in the old board in our BIOS, but we couldn't observe any changes on the eSPI using the SignalTap logic analyzer. These address ranges are as follows: 0x161E - 0x161F, 0x162E - 0x162F, 0x164E - 0x164F, and 0x0377 - 0x037F. However, using simulation, we were able to successfully perform RD/WR from these address ranges. We also tried using the eSPI to Agent IP, and also couldn't access these addresses. However, this IP also includes PORT00 - PORTA0 interfaces in its top entity. We could observe eSPI transactions from PORT60, PORT80, and PORT90, and were able to successfully WR and RD data to/from these ports. We came across a note in chapter 8 (eSPI to LPC Bridge Core) of the Embedded Peripherals IP User Guide that indicated that Bus Host IO Read/Write cycles are not supported. https://www.intel.com/content/www/us/en/docs/programmable/683130/21-3/unsupported-lpc-features.html So, my questions are: 1. Is this note related to our case? 2. Could you please recommend on how to proceed? Our ultimate goal is to be able to access the FPGA registers from the CPU using the address space that I mentioned above. Thank you. AviSolved2KViews0likes3CommentsRe: Cannot program QSPI memory through ASMI Parallel II IP
Hi Wincent, We didn't solve the problem yet. What I meant is that I am not sure that we need to include the Serial Flash Loader IP, since we already able to perform some Flash operations by just using the ASMI II IP, like reading from it, changing its status registers, and even erasing it (what means that the write enable bit was enabled), etc. But direct data write is not working for us. So, the QSPI pins must be toggled by the ASMI II IP during the operations that do work. I assume that the SFL is already embedded in the ASMI II IP. So, my question was if you still think that we need to include the SFL in our design? Thank you Avi2.1KViews0likes1CommentRe: Cannot program QSPI memory through ASMI Parallel II IP
Hi Wincent, First, thank you for your reply! If we are able to read QSPI memory data content, to erase the Flash, and to RD/WR to/from its status register using the ASMI II registers, isn't it means that the ASMI II IP has granted control on the SPI pins? Thank you Avi2.2KViews0likes0CommentsCannot program QSPI memory through ASMI Parallel II IP
Hello, We have a design that connects Avalon-MM Cyclone V Hard IP for PCIe Intel FPGA IP to ASMI Parallel II IP. The Cyclone V is connected to a QSPI serial Flash memory MT25QL512ABB8ESF (512Mb) Note that due to the 50MHz maximum clock frequency limitation of the ASMI II IP, we used an Avalon-MM Clock Crossing Bridge between the Avalon-MM Cyclone V Hard IP for PCIe and the ASMI II IP. The PCIe IP works at 125M, and the ASMI II works at 50MHz. We are able to modify the CSR at address 0x04010000 – 0x040100FF (e.g, perform WR_ENABLE, erase Flash sectors, and more), We are also able to read the Flash memory content. But we cannot program the Flash data at Addresses 0x00000000 – 0x03FFFFFF. From the ASMI Parallel II Intel® FPGA IP user guide we understand that, since there are no in-direct registers for address and data like was in the old ASMI IP, in this case in order to modify the Flash memory we should perform direct address-data write transactions, and the ASMI II IP will do the NOR programming sequence . But, as I wrote, it is not working.Solved2.3KViews0likes8CommentsRe: USB Blaster driver conflict with other FTDI kit
I'm also having the same problem of not being able to use the USB to serial together with the USB Blaster. There is a way to workaround Programming by disconnecting the USB to serial and re-attaching it after the programming was completed, but there is no way to use SignalTap since I need the serial port connected during the debugging... I've tried many Quartus driver versions, and the latest USB to serial driver, but it still doesn't work.9.9KViews1like1CommentMAX10 I/Os state after JTAG operation
Hi, Can anyone tell what happens to the MAX10 after JTAG operation? Its I/Os float, its flip flops being cleared, it gets DEV_CLR, etc We have two MAX10 devices on our board connected together on a chain. one of the FPGAs controls the board reset. We see that after every operation, even after "Verify" of one of the FPGAs (it doesn't matter which), our board gets reset. Thanks Avi1.3KViews0likes4Comments