eSPI to LPC bridge I/O transactions

Hello,

We are currently working on a new Intel SBC board that is based on legacy boards that utilized older Intel platforms like Coffee Lake. These legacy boards utilized an LPC bus to connect the PCH and FPGA device, with the PCH performing RD/WR operations from the FPGA registers through LPC I/O commands.

However, our new board, which includes the MAX10 FPGA, is based on the Tiger Lake CPU, which no longer supports the LPC bus and instead uses the eSPI bus. In an attempt to bridge the PCH's eSPI and the FPGA's LPC interface, we tried adding Intel's eSPI to LPC bridge. Unfortunately, this process has proven to be more challenging than anticipated.

We have opened the same LPC address ranges as in the old board in our BIOS, but we couldn't observe any changes on the eSPI using the SignalTap logic analyzer. These address ranges are as follows: 0x161E - 0x161F, 0x162E - 0x162F, 0x164E - 0x164F, and 0x0377 - 0x037F. However, using simulation, we were able to successfully perform RD/WR from these address ranges.

We also tried using the eSPI to Agent IP, and also couldn't access these addresses.
However, this IP also includes PORT00 - PORTA0 interfaces in its top entity. We could observe eSPI transactions from PORT60, PORT80, and PORT90, and were able to successfully WR and RD data to/from these ports.

We came across a note in chapter 8 (eSPI to LPC Bridge Core) of the Embedded Peripherals IP User Guide that indicated that Bus Host IO Read/Write cycles are not supported.

https://www.intel.com/content/www/us/en/docs/programmable/683130/21-3/unsupported-lpc-features.html

So, my questions are:

1. Is this note related to our case?

2. Could you please recommend on how to proceed? Our ultimate goal is to be able to access the FPGA registers from the CPU using the address space that I mentioned above.

Thank you.

Avi