SSD001
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NIOS II
Hi I am trying to implement a IPMI protocol using NIOS II processor (economic mode) in MAX 10 FPGA (10M16SAU324I7G). While running the design i am getting the following error. Is there any way to make the processor occupy LUT instead of the M9K memory. I have also attached the project file for reference. Error (170040): Can't place all RAM cells in design Info (170034): Selected device has 61 memory locations of type M9K. The current design requires 77 memory locations of type M9K to successfully fit. Info (170033): Memory usage required for the design in the current device: 126% M9K memory block locations required1.1KViews0likes2CommentsMAX 10 Ethernet Error
Hi Friends I am using a MAX 10 CPLD (10M16SAUI169I7G) which is connected to LS1012A processor using 10/100 Media independent Interface.The max10 is used for acquiring the data from the ADC based on the instruction from the CPU.The MAX10 does not receive the UDP packets from the processor at random time.The Triple speed Ethernet IP receiver is configured in promiscuous mode. ETHERNET IP CORE USED : Triple Speed Ethernet 18.1 CPLD Used : 10M16SAU169I7G Processor Used In Board : LS1012A Mode of Communication between in Processor and CPLD : Media Independent Interface 10/100 Software Tool used : Quartus Lite Version 18.1 IP Core : Triple Speed Ethernet CPU USED : NXP layerscape 1012A Low Power Communication Processor CPU Part number : LS1012A At the Time of the Ethernet hang i am receiving data at the PHY chip level but when i set the Trigger at ff_rx_sop (rising_edge) the Signal Tap analyzer the file says it in acquiring state as shown in the image below. With Regards S.D.Shandeep920Views0likes2CommentsRe: MAX 10 Ethernet not Responding
hi Dlim I am using TSE ip 18.1 version. The above problem is a random failure does not happen after a particular cycle. Never experience loss of packet or corrupted packet. It looks more like a hang issue. The Max10 IP core is connected to processor through PHY device(KSZ8081MNXIA-TR). The Ethernet resumes after reset is pressed sometimes but sometimes does not resume operation even after a power cycle. The rx_err[5:0] signal has been monitored but it does not show any errors so far in my observation.1.1KViews0likes0CommentsMAX 10 Ethernet not Responding
Hi I am using a MAX 10 CPLD (10M16SAUI169I7G) which is connected to LS1012A processor using 10/100 Media independent Interface. The MAX10 does not receive the UDP packets from the processor after running a operation of about 4 hours. The Triple speed Ethernet IP receiver is configured in promiscuous mode.1.1KViews0likes4CommentsMAX 10
MAX10 Hi I have some doubts regarding the Max10 CPLD (10M16SAU169I7). Does the Max 10 CPLD support the NIOS II economy. Can i use the Nios II economy processor to interact with four ADC and implement Three I2C modules for monitoring the temperature of the board. With Regards S.D.Shandeep923Views0likes3CommentsMAX10 NIOS II
Hi I have some doubts regarding the Max10 CPLD (10M16SAU169I7). Does the Max 10 CPLD support the NIOS II economy. Can i use the Nios II economy processor to interact with four ADC and implement Three I2C modules. From the Datasheet i understand that the device has a inbuilt ADC. Where can i find the example programs regarding the use of the inbuilt ADC present in the device. With Regards S.D.Shandeep609Views0likes1CommentTo achieve 2.5V output voltage on EN5339QI.
Hi all, We are using EN5339QI in many of our projects, In one of our project we have set EN5339QI to generate 2.5V output with 5V input. But when I probe at the output I could able to get only 0.7V only. Can you please help me to overcome the issue. Our load on 2.5V is 0.8A. Since it is an high priority project I request to help me as soon as possible. Hereby attaching the schematics of EN5339QI for your reference. Thank you. Amarnath G (g.amarnath17@gmail.com)1.2KViews0likes1Comment