SSD001
New Contributor
5 years agoMAX 10 Ethernet Error
Hi Friends
I am using a MAX 10 CPLD (10M16SAUI169I7G) which is connected to LS1012A processor using 10/100 Media independent Interface.The max10 is used for acquiring the data from the ADC based on the instruction from the CPU.The MAX10 does not receive the UDP packets from the processor at random time.The Triple speed Ethernet IP receiver is configured in promiscuous mode.
ETHERNET IP CORE USED : Triple Speed Ethernet 18.1
CPLD Used : 10M16SAU169I7G
Processor Used In Board : LS1012A
Mode of Communication between in Processor and CPLD : Media Independent Interface 10/100
Software Tool used : Quartus Lite Version 18.1
IP Core : Triple Speed Ethernet
CPU USED : NXP layerscape 1012A Low Power Communication Processor
CPU Part number : LS1012A
At the Time of the Ethernet hang i am receiving data at the PHY chip level but when i set the Trigger at ff_rx_sop (rising_edge) the Signal Tap analyzer the file says it in acquiring state as shown in the image below.
With Regards
S.D.Shandeep