MAX 10 Ethernet Error

Hi,

From your signal_tap debug, that means it doesn't detect any assertion of ff_rx_sop signal. Nothing is coming out from TSE MAC Rx to FPGA core logic

• It's either something is already corrupted from PHY Rx to FPGA Rx side
• or some issue with your signal_tap sampling clock (fpga_mii_tx_clk)

You can set signal_tap trigger condition to "don't care" stage instead of trigger rising edge

Also you can probe TSE rx_err[5:0] to try identify what kind of error that you are facing

Another common debug approach is to enable TSE internal loopback to isolate whether the issue is inside FPGA or outside on your board setup

Thanks.

Regards,

dlim