iiwan
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Stratix V GT LL PHY TTK
I need to test Stratix V GT transceiver channels at speed 27 Gbps. At that speed I can only use Low Latency PHY IP core. It has own avalon slave and reconfig xcvr bus. I tried to use both to connect to JTAG to Avalon master bridge but did not get any results. And did not find any example design for my use case. For Arria 10 I found a lot of designs, but there are everything in IP core, all things as ADME and PRBS. Any help please.898Views0likes2CommentsRe: Native phy simulation
I see, that reconfig_reset is 1, and rx_locktodata and rx_locktoref is 0. I never sim native phy, but at hardware if this signals are 0, i think that it does not generate you rx_clkout. And I think if tx_clkout is good, that means, that refclk is good. And I think you have to send some serial to your rx_serial_data at high freq clock.1.1KViews0likes0CommentsHierarchical partial reconfiguration
I am interested in PR in Arria 10. For example, I have 4 same PR regions with 4 same PR personas in each. So can I make 4 PR rbf files somehow, that will i use to reconfig each region separately. After reading base manuals, I understand that I can make 16 rbf files and reconfig or reconfig my PR regions at the same time equally. Any help please, to understand. In other words, I want to have 4 rbf files and use them independently to rebuild the logic of my 4 PR regions.Solved1.1KViews0likes1CommentArria 10 transceivers speed grade
I am testing Arria 10 GX with transceivers speed grade 3, and have enabled in native phy standard pcs(8b/10b decorer and encoder and word aligner). Does pcs downgrade speed of my Transceivers? In device datasheet I did not find information about it. In Stratix V daasheet this thing was described. And what is difference in chip to chip and backplane? For example I have board with sfp modules? Is this backplane or not?886Views0likes2CommentsATX PLL profile reconfiguration
I need in my design for Arria 10 to reconfigure ATX PLL with 3 profiles, 1250,2500,5000 MHz output clock. Configured profiles, enabled embedded streamer and everything other needed as in xcvr user guide. Also I added jtag_to_avalon_master_bridge. Connected with reconfiguration pins of ATX PLL. And reconfiguration via system console does work. Profiles does not change. But if I remove jtagtoavalonMB and add internal jtag debug master in ATX PLL reconfiguration with profiles works good. At the end of test I will use my own logic with reconfiguration, not with system console.And my own logic does not work too. I could not find problem and need help. May be after reconfiguration I have to send mgmt_reset of reconfiguration? Or something not mentioned in documentation?1.5KViews0likes6Comments