iiwan
New Contributor
New ContributorArria 10 Native Phy Settings
I am new to Arria 10. When I configured TX PMA, did not find TX PLL clock frequently to choose, as It was in Stratix V. So Arria 10 uses RxRefClk for TX PLL? Or how have I to configure? My clk is sa...
Hi,
As I understand it, you have some inquiries related to A10 XCVR instantiation. Please see my responses as following:
1. In Arria 10, the TX PLL ie ATX PLL is instantiated separately and connect to Native PHY
2. User would need to build own byte ordering block in core logic. Sorry for the inconvenience.
Please let me know if there is any concern. Thank you.
