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iiwan's avatar
iiwan
Icon for New Contributor rankNew Contributor
5 years ago

Arria 10 transceivers speed grade

I am testing Arria 10 GX with transceivers speed grade 3, and have enabled in native phy standard pcs(8b/10b decorer and encoder and word aligner).

Does pcs downgrade speed of my Transceivers? In device datasheet I did not find information about it. In Stratix V daasheet this thing was described.

And what is difference in chip to chip and backplane? For example I have board with sfp modules? Is this backplane or not?

2 Replies

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    PCS speedgrade is tied to transceiver speedgrade as PCS is part of transceiver channel design block.


    For chip to chip :

    • This is like referring to FPGA transceiver connect to another chip transceiver directly
    • Board A (FPGA) <-> Board B (chip)


    For backplane :

    • This is referring to system application where FPGA transceiver connect to another backplane board (via some connector) and then to another chip on another board
    • Board A (FPGA) <-> Backplane board <-> Board B (chip)


    I am not sure how your QSFP module connect to the other end destination of your system setup but I hope my explanation is clear to you.


    Thanks.


    Regards,

    dlim


  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    HI,


    I hope I have clarified your questions on Aug 24 feedback.


    For now, I am setting this case to closure.


    Regards,

    dlim