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ShafiqY_Intel

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Joined 7 years ago

489 Posts15 LikesLikes received14 Solutions

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Re: Intel FPGA on board USB Blaster example design
Hi, I already sent you a private message. Please go to top right (refer picture below) ---> go to inbox. Thanks Regards, Matt
5 years ago Place IP & Transceiver
3.1KViews
0likes
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Re: Quartus Prime Lite 20.1 "Can't recognize silicon ID for device <name>" for EPCQ64-A, EPCQ128-A
Hi TJLW, Have you tried to use the Quartus standard version 18.1 or 19.1? Regards, Matt
5 years ago Place Quartus® Prime
1.2KViews
0likes
0Comments
Re: Intel FPGA on board USB Blaster example design
Hi gyuunyuu, Please contact me via private message. I'll continue support you vie private message. Thanks. Matt
5 years ago Place IP & Transceiver
3.1KViews
0likes
2Comments
Re: Clock out pin cannot be assigned 3.0V I/O bank.
Hi YFuji17, It's seem like you not assigned the pin properly. May I know your Cyclone 10 GX OPN number? And can you screenshot your pin planner and send it here? Thanks. Regards, Matt
5 years ago Place Quartus® Prime
1.2KViews
0likes
0Comments
Re: expected stdout device name does not match the selected target byte stream device name
Hi JPark222, If I not mistaken, this warning can be ignorable. Did your device program properly if you ignore this warning? Regards, Matt
5 years ago Place Nios® System
2.1KViews
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Re: Cyclone V - LVDS input on a bank with Vccpd=2.5V and Vccio=1.8V
Hi Zak, For LVDS inputs the requirements is Vccio=Vccpd For LVDS outputs the requirements is Vccio=2.5V And for Cyclone V, the value for Vccpd is 2.5V Regards, Matt
5 years ago Place FPGA Device
2.6KViews
2likes
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Re: Perturbations on altera cyclone IV e configuration signals
Hi LauraC, If the nCONFIG is driven LOW in short amount of time, the FPGA will go to RESET state. And the USER I/Os are tri-stated until the device enters user mode. Thanks. Regards, Matt
5 years ago Place FPGA Device
992Views
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Re: Looking for Altera EPC1LC20N programming SPEC
Hi anitachou, The EPC1 device is obsolete/discontinued support. Therefore, I could not find any document of you request in our internal database. I'm apologize for inconvenience. Thanks Regards, Matt
5 years ago Place FPGA Device
1.3KViews
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Re: how to use GPIOs in ddr3l bank
Hi XG_Kang, May I know how you're implementing the controller, is it soft or hard? As mentioned above, if it is hard, you may not be able to use other pins in that I/O bank as GPIO Regards, Matt
5 years ago Place Boards & Dev Kits
1.1KViews
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Re: Quartus Prime Programmer Pro Edition (19.3.0) crashes when Auto Detect is clicked
Hi Mustafa, Intel Quartus Prime software did not support OS CentOS Linux. Please refer to following link for Intel Quartus supported Operating System(OS): https://www.intel.com/content/www/us/en/programmable/support/support-resources/download/os-support.html Regards, Shafiq
5 years ago Place Quartus® Prime
2.2KViews
0likes
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