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Re: Enable on-chip termination for Differential Transceiver clocks
As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to https://supporttickets.intel.com/s/?language=en_US , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.1.7KViews0likes0CommentsRe: Agilex 5 Transceiver Tx failing for pll lock
Thanks for the update, I now transition this thread to community support. If you have a new question, Please login to https://supporttickets.intel.com/s/?language=en_US , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.930Views0likes0CommentsRe: Agilex 7 i series serdes capability
As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to https://supporttickets.intel.com/s/?language=en_US , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.769Views0likes0CommentsRe: Enable on-chip termination for Differential Transceiver clocks
Hi The error indicates that the "DIFFERENTIAL 100 OHM" termination assignment is not valid for your specific Arria 10 transceiver pins. You may check the value in link https://www.intel.com/content/www/us/en/docs/programmable/683084/current/xcvr-a10-rx-term-sel.html Values R_EXT0 R_R1 R_R2 The syntax would be: set_instance_assignment -name XCVR_A10_RX_TERM_SEL -to clk_xcvr_1f -entity myDesign R_R11.8KViews0likes1CommentRe: Agilex 5 Transceiver Tx failing for pll lock
Hi Thanks for your update. Here are some suggestions that may be best for next steps: · The 1562500 reading may indicate a clocking mismatch. Since you saw changes by adjusting the PMA ref clock, it suggests that the clock path is responsive but may still not match DisplayPort requirements. Confirm the frequency aligns with DisplayPort's expected 1.62, 2.7, 5.4, or 8.1 Gbps configurations. · Switching to a standard GTS PHY may offer more flexibility for low-level debugging and clock alignment, but it could add complexity if specific DisplayPort optimizations are needed. If the reconfiguration limitations persist, testing with the GTS PHY might help isolate the issue.966Views0likes1CommentRe: Unable to generate Transceiver IP for PCIe Gen6 PAM-4 64 GT/s rate on Intel Agilex-7 FPGA
As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to https://supporttickets.intel.com/s/?language=en_US , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.581Views0likes0CommentsRe: Enable on-chip termination for Differential Transceiver clocks
Hi Based on my understanding, When Quartus detects an unrecognized or unsupported .qsf syntax, it typically ignores it without generating a critical error—unless the syntax affects an essential function that would cause the design to fail timing or functionality checks. In your case, Quartus likely ignored the unsupported HSSI_PARAMETER syntax and instead applied its default settings for differential transceiver clocks, which can sometimes include internal terminations if the clock configuration implicitly supports it. In Arria 10, the differential transceiver clocks often have default terminations based on common transceiver configurations. Since 100-ohm differential termination is typical for many high-speed applications, Quartus may have automatically applied this setting, even with the syntax error.1.9KViews0likes1CommentRe: Agilex 7 i series serdes capability
Hi For the Agilex 7 I-Series FPGA device with part number AGIB027R31B1E1VAA, reference board files for the DK-SI-AGI027FB development kit should be available through the Intel Agilex development kit documentation. You can access these resources under Intel's Agilex Development Kits. This link provides information on the Agilex AGF027 and AGF023 kits, and Table 3 within the documentation often includes links to board files and configuration guides. The link is a helpful starting point for understanding the device's capabilities. · https://www.intel.com/content/www/us/en/products/details/fpga/agilex/7/item.html · https://www.intel.com/content/www/us/en/content-details/779615/agilex-7-fpga-i-series-116-gbps-pam4-lr-transceiver-overview.html For reference eye diagrams at specific data rates, the Intel Agilex Transceiver PHY User Guide typically details performance metrics like the supported data rate ranges of 1-32 Gbps NRZ and 20-58.125 Gbps PAM4 for FGT PMAs. If these diagrams aren’t included in the public documentation, you may request it through your distributor. Refer link https://www.intel.com/content/www/us/en/partner/where-to-buy/overview.html863Views0likes0CommentsRe: Agilex 5 Transceiver Tx failing for pll lock
Hi It looks like you're encountering a clocking issue with the DisplayPort IP on Agilex 5 where the Transceiver Tx PLL fails to lock, particularly affecting your near-side loopback testing. To proceed, consider these steps: Review PLL Configuration: Verify that the Tx PLL settings match the clock requirements of your DisplayPort application, as minor mismatches can lead to locking issues. Check PMA Direct Clocking: Ensure PMA direct clocking is configured properly in Quartus, as mismatches here could impact Tx lock performance, especially on banks 4B and 4C. Clock Signals and Layout: Double-check if the clock signal integrity and layout of your design match the specifications for both Rx and Tx paths, as these can impact PLL locking stability, especially at the high data rates used for DisplayPort.1.1KViews0likes1CommentRe: Unable to generate Transceiver IP for PCIe Gen6 PAM-4 64 GT/s rate on Intel Agilex-7 FPGA
For PCIe Gen6 support on Agilex-7, the recommended is using devices equipped with F-Tile, specifically those that include FHT PMAs, as these are optimized for high-speed applications like PCIe Gen6.676Views0likes0Comments