Agilex 5 Transceiver Tx failing for pll lock

Hi

Thanks for your update. Here are some suggestions that may be best for next steps:

· The 1562500 reading may indicate a clocking mismatch. Since you saw changes by adjusting the PMA ref clock, it suggests that the clock path is responsive but may still not match DisplayPort requirements. Confirm the frequency aligns with DisplayPort's expected 1.62, 2.7, 5.4, or 8.1 Gbps configurations.

· Switching to a standard GTS PHY may offer more flexibility for low-level debugging and clock alignment, but it could add complexity if specific DisplayPort optimizations are needed. If the reconfiguration limitations persist, testing with the GTS PHY might help isolate the issue.