Agilex 5 Transceiver Tx failing for pll lock

Hi

It looks like you're encountering a clocking issue with the DisplayPort IP on Agilex 5 where the Transceiver Tx PLL fails to lock, particularly affecting your near-side loopback testing.

To proceed, consider these steps:

Review PLL Configuration: Verify that the Tx PLL settings match the clock requirements of your DisplayPort application, as minor mismatches can lead to locking issues.

Check PMA Direct Clocking: Ensure PMA direct clocking is configured properly in Quartus, as mismatches here could impact Tx lock performance, especially on banks 4B and 4C.

Clock Signals and Layout: Double-check if the clock signal integrity and layout of your design match the specifications for both Rx and Tx paths, as these can impact PLL locking stability, especially at the high data rates used for DisplayPort.