New Contributor
Super ContributorHi
It looks like you're encountering a clocking issue with the DisplayPort IP on Agilex 5 where the Transceiver Tx PLL fails to lock, particularly affecting your near-side loopback testing.
To proceed, consider these steps:
Review PLL Configuration: Verify that the Tx PLL settings match the clock requirements of your DisplayPort application, as minor mismatches can lead to locking issues.
Check PMA Direct Clocking: Ensure PMA direct clocking is configured properly in Quartus, as mismatches here could impact Tx lock performance, especially on banks 4B and 4C.
Clock Signals and Layout: Double-check if the clock signal integrity and layout of your design match the specifications for both Rx and Tx paths, as these can impact PLL locking stability, especially at the high data rates used for DisplayPort.
New ContributorHi,
Many thanks for your inputs.
In your comments, you have mentioned "Verify that the Tx PLL settings match".
However, the DP PHY as generated from the example design for Agilex5 does not show any option for the Tx PLL configuration.
Havinf said that, I have managed to get the Tx pll locked after tweaking a few parts of the code in NIOS.
However, the DP links are still not connecting to a Monitor (source) or a PC (sink).
For ease of debugging I have now reduced the Link speed from 8.1Gbps to 5.4Gbps.
With the use of debug registers (mr_rate_detect.v ) I now see that the 23 bit DP clock speed monitor register is set to a value of 1562500 which does not seem to be the standard DP clock frequency.
I have set my PMA ref clock to 150MHz (Tx and Rx) for both Bank 4B and Bank 4C.
For the sake of experimenting, to see if the clock configuration was working, I have tried changing the PMA ref clock to 144MHz and saw the clock speed chanigning accordingly ( to 1500000).
Please see below the GST Display Port Phy paramters available to me. I do not see any valid address range to access the GTS PHY reconfiguration registers. There seems to be hidden management port interface that seems to be magically connnected to DisplayPort IP
Would you recommend that I replace the DisplayPort Phy with the normal GTS PHY ?
Best Regards,
