remov_b4_flight
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Compile option not saved (reversed to default)
Quartus std 25.1 / Questa Altrera FPGA Ed. 64 2025.2 My project use systemverilog all designs. launch RTL Simulation/Questa from Quartus , Everytime error happen not treated as designs are systemverilog. Opening "Compile->Compile option->verilog" and chage "default" to "systemverilog" then re-load design by "do ***_run_msim_rtl_systemverilog.do" command, no error happens. But next Questa launch, same error happend and "Compile option" reversed to "default" not saved.Re: Warning at Standard 25.1 by Arria 10
My concern is that Arria 10 support will be removed from the Standard version in the future. You might say that I could just use 25.3 Pro, but even with 25.3 Pro with the 0.27 patch, crashes continue to occur during elaboration. For the time being, we plan to use 25.1 Standard for the project we are developing, but I am worried that when we need the optimization features of the Pro version, there will be no Pro version available. I would like Altera to be transparent about device and development tool support. I hope that the current situation is temporary.Warning at Standard 25.1 by Arria 10
Hi all. recent Queatus Prime Pro 25.3.1 drops Arria 10 support. (no Arria 10 support files in individual download page) But latest Standard 25.1 warns at compile Arria 10 project, by these message Info (24153): Support for Arria 10 devices is deprecated in the Quartus Prime Standard Edition software. For new Arria 10 designs, use the Quartus Prime Pro Edition software. For existing Arria 10 designs, continue to use the Quartus Prime Standard Edition software. Is this due to the difference in release dates between 25.3.1 and 25.1? Will we no longer see this warning when Standard 25.3 is released in the near future?'*.vho not found' in Modelsim ALTERA
Dear sirs, At QuartusII 13.1 / Stratix3 project, "DDR3 SDRAM Controller with UniPHY" IP on our design. I finished synthesys and run modelsim 10.1d for RTL simulation, After launched modelsim and do jobs in transcript window until 1st prompt. I got error: # vcom -93 -work work {*PATH*/*TO*/*PROJ/*IP_name*.vho} # Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012 # ** Error: (vcom-7) Failed to open design unit file "*PATH*/*TO*/*PROJ*/*IP_name*.vho" in read mode. Certainly do not have *.vho (IPFS FILES ?) file. How to generate it and run simulation?
