kmzaja
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aocl_mmd_read() and aocl_mmd_write() for memory movement
Hello, I am using Intel's oneAPI with my Agilex FPGA accelerator. I need help with something on a lower level of abstraction w.r.t libraries being used in oneAPI. I need to use MMD API calls for accessing my AFU kernel and the local memory on FPGA. I have been able to access my AFU kernel but I am struggling with accessing the local memory (DDR in this case). Unfortunately, I could not find example codes of MMD APIs and oneAPIs documentation also does not contains much information on this. Whenever I am trying to read/write into my local memory using MMD APIs, I either get alignment error or segmentation fault. For accessing DDR4, is there a specific buffer/array to use for reading/writing? For example, I am using malloc to create read/write buffers. Is there some other function to use for this. Also, for my BSP, UVM is disabled. So maybe I cannot use the aocl_mmfd_shared_alloc function call from MMD API. Thank you in advance and I can share more details if/when required. Few details: OS: AlmaLinux Board: Bittware Agliex7 FPGA board BSP: OFS basedError while applying quartus patches
I am working with a third-party vendor's intel FPGA board and for my application I am trying to apply patches on my quartus, but I am facing issues in it: I get two more errors which I think are resultant of this. Is there something I am missing? I am giving following directory for patch installation: <quartus_installation_directory_path>/bin Because of limited tool support for my FPGA, I am working with: OS: AlmaLinux 9 Quartus: Prime pro version 21.4Re: What is it about CCI-P and why there is no Dev kit compatible FIM (FPGA Interface Manager)?
Any comments on this? For my first question, I think I have found the answer (please correct me if I am wrong). Even though intel docs are specific to Xeon processor as host but it is not a hard requirement. Host CPU can be different. It is just the verification part that is only being performed by the Xeon processor. Link to the answer: https://community.intel.com/t5/Application-Acceleration-With/openFPGA-Stack-Requires-Xeon/m-p/1612307#M2586 I am still looking for the answer for my second question. Is it possible to develop FIM for a development kit? Has anyone tried this? I am using Arria10 FPGA dev kit for my project. Regards,What is it about CCI-P and why there is no Dev kit compatible FIM (FPGA Interface Manager)?
Maybe this question belongs to Application Acceleration with FPGAs. I am learning about GPUs and currently trying to run this vortex project on a FPGA. I came across a lot of new terminologies, libraries and tools in the process. So, my questions are pretty basic (or maybe not?) but I couldn't find much help on this and thus asking here. Question 1: Why CCI-P is specific to Intel Xeon processor? Isn't it just a protocol for communication between FIU/FIM and AFU. And FIU then communicates with the host channel and the local memory? So, in this case does it matter what host CPU I am using? Question 2: All intel documents on FIM (and even on CCI-P) are very specific to Intel Xeon with integrated FPGA and/or Intel PAC. I have this impression that maybe because FIM cannot be synthesized on development kits? And if yes, why? It is very likely that my understanding on the above topics is totally incorrect and I am open for any correction in this regard. Please share your views or even any links/blogs that will help me to understand these topics better. Thank you!
