JackDalton
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Timing Violations: 8x F-Tile ETH Hard IP TX_CLKOUT
Hello Intel Team, In our design, we instantiated eight 10G F-Tile Ethernet Hard IPs (including ANLT) using the VHDL "GENERATE" construct. During timing analysis, we are encountering setup and hold violations on the "TX_CLKOUT" path of the F-Tile transceivers. The "REPORT_CLOCKS" command shows that these 8 clocks are being generated with a frequency of 402.83 MHz under the following names: gen_eth[0].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch23 gen_eth[1].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch22 ... gen_eth[7].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch16 The corresponding master clocks are: gen_eth[0].proc_ftile_eth_hardip|eth_f_0|tx_pld_pcs_clk_reg|ch23 TX_CLKOUT clocks are asynchronous to each other and operate independently. Therefore, we attempted to exclude them from timing analysis using the "set_clock_groups -asynchronous" constraint, like this: set_clock_groups -asynchronous \ -group { [get_clocks {gen_eth[0].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch23}] } \ -group { [get_clocks {gen_eth[1].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch22}] } \ -group { [get_clocks {gen_eth[2].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch21}] } \ -group { [get_clocks {gen_eth[3].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch20}] } \ -group { [get_clocks {gen_eth[4].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch19}] } \ -group { [get_clocks {gen_eth[5].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch18}] } \ -group { [get_clocks {gen_eth[6].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch17}] } \ -group { [get_clocks {gen_eth[7].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch16}] } However, this approach results in the following errors: - Warning(20314): Invalid collection filter: [get_clocks {gen_eth[0].proc...}] - Warning(332049): Ignored set_clocks_group: Argument -group with value could not match any element of the type clk. - Warning(332049): Argument -group is not an obejct ID. I’ve tried multiple approaches, get_nets, Get_pins, also using wildcards and "create_generated_clock", but nothing has resolved the issue. According to my understanding, a "create_generated_clock" constraint shouldn't be necessary, since these clocks are automatically generated by Quartus. When inspecting the design in the Timing Analyzer using "get_clocks *ch23, the clock names appear to be internally resolved to autogenerated IDs like "_co15660". However, these IDs are not stable and may change with each compile (fit), which makes them unsuitable for constraints. At this point, I am running out of ideas. Question: How can I properly constraint or eliminate the setup and hold violations on the eight "TX_CLKout" clocks generated by Quartus in the F-Tile Ethernet Hard IPs? Should I just use "Set_False_Path"? I used the "Generate" command in VHDL to instantiate the 8 F-Tile ETH Hard IP + 8 ANLT. Could be this a problem ? kind regards JacobRe: Adding generated IPs as library in Questa
Running "msim_setup.tcl" created the corresponding library directories, but they are empty. What is missing is the "fifo_1927" library. How do you integrate the library into Questa from the generated IP? What is missing ? The help "Design Simulations" and "Introduction to FPGA IPs" did not provide any new insights for me. kind regards Jack daltonRe: Simulator Support Agilex PCIe R-Tile Gen5 1x16
Hi VenTingT, We ordered an Eval board with an Agilex 7 I-Series FPGA. The PCIe core should also be used in the R-Tile. If the Modelsim Simualtor is no longer supported as of Quartus 21.3, which simulator do you recommend for the PCIe IP Core R-tile simulation ? kind regards Jack DaltonSimulator Support Agilex PCIe R-Tile Gen5 1x16
Hello, Which simulators are supported for a PCIe Agilex R-Tile simulation? VCS*, VCS* MX, Siemens EDA QuestaSim*, and Xcelium* are the only simulators supported in the latest release of Intel® Quartus® Prime. Note: The Xcelium* simulator support is only available in Production devices or Engineering Samples with the following OPNs: AGIx027R29AxxxxR2 AGIx027R29AxxxxR3 AGIx027R29BxxxxR3 AGIx023R18AxxxxR0 AGIx041R29DxxxxR0 AGIx041R29DxxxxR1 AGMx039R47AxxR0 Can Intel Mentor Modelsim FPGA Starter be used to simulate Agilex R-Tile Gen5 1x16 ? Kind regards Jack Dalton
