Forum Discussion
JackDalton
New Contributor
New ContributorTiming Violations: 8x F-Tile ETH Hard IP TX_CLKOUT
Hello Intel Team, In our design, we instantiated eight 10G F-Tile Ethernet Hard IPs (including ANLT) using the VHDL "GENERATE" construct. During timing analysis, we are encountering setup and hold v...
JackDaltonNew Contributor
New ContributorHello,
is the problem perhaps too obvious ?
The F-Tile manual couldn't give me any clues.
What have I missed?
I would appreciate a quick hint.
I would also like to add that we are using the Agilex 7 i-series with Quartus 25.1.
kind regards
Jack
