allen18
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Re: The Quartus Prime software quit unexpectedly！
I cannot upload the QAR file as an attachment because the file is encrypted on my computer. I suspect this issue might relate to the computer's performance, as my current 8-core processor consistently reaches 100% CPU usage during the filter phase. I cannot confirm whether the latest version of Quartus has the same problem yet and will continue monitoring. Perhaps this issue can be closed for now.Re: The Quartus Prime software quit unexpectedly！
This issue tends to occur probabilistically during the filter process when CPU and memory usage becomes excessively high. I attempted to mitigate it by limiting the number of CPU cores allocated for compilation, but the problem still recurred several times afterward. I have not yet upgraded to the latest Quartus version because a significant number of IP cores would require simultaneous upgrades, which complicates the process.Re: Stratix10 PCIe clock structure issue
Hi ventt, Thank you for your reply. My qsf file is derived from the example design. Since the file was encrypted, I have copied its contents here. I believe there should not be significant differences between our QSF files. Our current project can proceed using a common reference clock, so this issue does not affect the project timeline. Your test results have proven that the example design can run normally on the development board, I suspect the problem might stem from either my current environment’s clock not meeting the reference clock requirements or potential PCB signal integrity issues. Could you provide the qar file for your current project? Then perhaps we can close this issue. Thanks. """ set_global_assignment -name ORIGINAL_QUARTUS_VERSION 22.3.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:13:13 NOVEMBER 07, 2024" set_global_assignment -name LAST_QUARTUS_VERSION "22.3.0 Pro Edition" set_global_assignment -name FAMILY "Stratix 10" set_global_assignment -name DEVICE 1SX110HN2F43I2VG set_global_assignment -name VERILOG_MACRO "ALTERA_EMIF_ENABLE_ISSP=1" set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4" set_global_assignment -name USE_PWRMGT_SCL SDM_IO14 set_global_assignment -name USE_PWRMGT_SDA SDM_IO11 set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 40 set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name TOP_LEVEL_ENTITY pcie_ed set_global_assignment -name IP_FILE ip/pcie_ed/pcie_ed_DUT.ip set_global_assignment -name IP_FILE ip/pcie_ed/pcie_ed_resetIP.ip set_global_assignment -name IP_FILE ip/pcie_ed/pcie_ed_MEM.ip set_global_assignment -name QSYS_FILE pcie_ed.qsys set_location_assignment PIN_AT34 -to refclk_clk set_location_assignment PIN_AT33 -to "refclk_clk(n)" set_location_assignment PIN_AW32 -to xcvr_rx_in3 set_location_assignment PIN_AW31 -to "xcvr_rx_in3(n)" set_location_assignment PIN_BB30 -to xcvr_rx_in2 set_location_assignment PIN_BB29 -to "xcvr_rx_in2(n)" set_location_assignment PIN_AY30 -to xcvr_rx_in1 set_location_assignment PIN_AY29 -to "xcvr_rx_in1(n)" set_location_assignment PIN_AV30 -to xcvr_rx_in0 set_location_assignment PIN_AV29 -to "xcvr_rx_in0(n)" set_location_assignment PIN_AY38 -to xcvr_tx_out3 set_location_assignment PIN_AY37 -to "xcvr_tx_out3(n)" set_location_assignment PIN_BB38 -to xcvr_tx_out2 set_location_assignment PIN_BB37 -to "xcvr_tx_out2(n)" set_location_assignment PIN_BA36 -to xcvr_tx_out1 set_location_assignment PIN_BA35 -to "xcvr_tx_out1(n)" set_location_assignment PIN_BB34 -to xcvr_tx_out0 set_location_assignment PIN_BB33 -to "xcvr_tx_out0(n)" set_instance_assignment -name IO_STANDARD LVDS -to refclk_clk -entity pcie_ed set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to xcvr_tx_out0 -entity pcie_ed set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to xcvr_rx_in0 -entity pcie_ed set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to xcvr_tx_out1 -entity pcie_ed set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to xcvr_rx_in1 -entity pcie_ed set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to xcvr_tx_out2 -entity pcie_ed set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to xcvr_rx_in2 -entity pcie_ed set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to xcvr_tx_out3 -entity pcie_ed set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to xcvr_rx_in3 -entity pcie_ed set_location_assignment PIN_AC26 -to pcie_rstn_pin_perst set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to pcie_rstn_pin_perst -entity pcie_ed """The Quartus Prime software quit unexpectedly！
I frequently encounter this error during project compilation, which typically occurs during the filter process and happens after several hours of compiling. It severely wastes time and reduces work efficiency. Has anyone experienced the same issue? """ Problem Details Error: *** Fatal Error: Access Violation at 00007FFAB99D4EF0 Module: quartus_fit.exe Stack Trace: Quartus 0x104eef: RTM_COMMON_TIMING_ANALYSIS::EDGE_REQS::set_second_req + 0xf (tsm_rtm) Quartus 0x10a2b0: std::vector<std::pair<QTL_SMALL_VECTOR<unsigned int,std::allocator<unsigned int> >,RTM_COMMON_TIMING_ANALYSIS::EDGE_REQS>,std::allocator<std::pair<QTL_SMALL_VECTOR<unsigned int,std::allocator<unsigned int> >,RTM_COMMON_TIMING_ANALYSIS::EDGE_REQS> > >::vector<std::pair<QTL_SMALL_VECTOR<unsigned int,std::allocator<unsigned int> >,RTM_COMMON_TIMING_ANALYSIS::EDGE_REQS>,std::allocator<std::pair<QTL_SMALL_VECTOR<unsigned int,std::allocator<unsigned int> >,RTM_COMMON_TIMING_ANALYSIS::EDGE_REQS> > > + 0xd0 (tsm_rtm) Quartus 0x10ea55: RTM_COMMON_TIMING_ANALYSIS_ITERATOR::generate_tdb_clock_data_per_edge_cache + 0x115 (tsm_rtm) Quartus 0x1814a4: RTM_RACAD_TIMING_ANALYSIS::perform_racad_timing_analysis + 0x94 (tsm_rtm) Quartus 0x1733e5: `anonymous namespace'::MIN_REG_FINDER<0>::pre_traversal + 0x6005 (tsm_rtm) Quartus 0x16b8fd: `anonymous namespace'::IMPLIED_RESTRICTION_FINDER::load_queue + 0x206d (tsm_rtm) Quartus 0x71c3c: `anonymous namespace'::register_nvd_to_qhd + 0x7dac (tsm_rtm) Quartus 0x473bc: (TSM_TDC) Quartus 0x1114b: (TSM_TDC) Quartus 0x30e09: (TSM_FTI) Quartus 0x33e85: (TSM_FTI) Quartus 0x525cf7: (fitter_vpr20kmain) Quartus 0x501102: (fitter_vpr20kmain) Quartus 0x5031fb: (fitter_vpr20kmain) Quartus 0x50371a: (fitter_vpr20kmain) Quartus 0x3e539a: (fitter_vpr20kmain) Quartus 0x37ef44: (fitter_vpr20kmain) Quartus 0x2bf762: (fitter_vpr20kmain) Quartus 0x2ba52f: (fitter_vpr20kmain) Quartus 0x320b51: (fitter_vpr20kmain) Quartus 0x224ec9: (fitter_vpr20kmain) Quartus 0x2246b6: (fitter_vpr20kmain) Quartus 0x223bec: (fitter_vpr20kmain) Quartus 0x49216a: (fitter_vpr20kmain) Quartus 0x105204: (fitter_fdrgn) Quartus 0x100ded: (fitter_fdrgn) Quartus 0x26a2e: (comp_fit2) Quartus 0x16442: (tcl86) Quartus 0x532a: (comp_fit2) Quartus 0x16442: (tcl86) Quartus 0x17c4d: (tcl86) Quartus 0xa6a8b: (tcl86) Quartus 0xa5136: TclFSCwdIsNative + 0xffffffffffffff56 (tcl86) Quartus 0x22200: qexe_do_tcl + 0x1cd0 (comp_qexe) Quartus 0x20df2: qexe_do_tcl + 0x8c2 (comp_qexe) Quartus 0x29f51: qexe_run + 0xe81 (comp_qexe) Quartus 0x2973f: <lambda_f9491598d3e86dee3a670fcdbeed20e4>::operator() + 0x319f (comp_qcu) Quartus 0x391de: qcu_process_implied_register_optimization_assignments + 0x151e (comp_qcu) Quartus 0x296c9: qexe_run + 0x5f9 (comp_qexe) Quartus 0x2aa0a: qexe_run + 0x193a (comp_qexe) Quartus 0xbba2: <lambda_9f91090ffa5a337905f0d5d738529902>::operator()<> + 0x8c52 (quartus_fit) Quartus 0x27b68: std::`dynamic atexit destructor for '_Fac_tidy_reg'' + 0x23e3c (CCL_MSG) Quartus 0x28b22: std::`dynamic atexit destructor for '_Fac_tidy_reg'' + 0x24df6 (CCL_MSG) Quartus 0x2aae3: `anonymous namespace'::mem_tcmalloc_tracker_new_hook + 0x153 (ccl_mem) Quartus 0x25088: std::`dynamic atexit destructor for '_Fac_tidy_reg'' + 0x2135c (CCL_MSG) Quartus 0xcd2f: __scrt_common_main_seh + 0x10b (quartus_fit) Quartus 0x17c23: BaseThreadInitThunk + 0x13 (KERNEL32) Quartus 0x6d720: RtlUserThreadStart + 0x20 (ntdll) End-trace Executable: quartus Comment: None System Information Platform: windows64 OS name: Windows 10 OS version: 10.0 Quartus Prime Information Address bits: 64 Version: 22.3.0 Build: 104 Edition: Pro Edition """Re: Stratix10 PCIe clock structure issue
Hi ventt, I am currently unable to determine whether the issue is caused by my local environment, such as clock quality. Can you try running an Example Design in your environment ? Select PCIe avmm as the IP and set the slot clock configuration to OFF. Thanks.Re: Stratix10 PCIe clock structure issue
Hi ventt, I'm not using DEV kit. I cannot provide a complete schematic file but I can confirm that both reference clocks are valid and that the PCIe pin connections are correct, because when using the first set of reference clocks, DMA data transmission and reception can be performed normally. In UG, it can be seen that when using an independent reference clock, the slot clock configuration should be set to OFF, but I do this, the situation did not change much. When I use the second set of parameter clocks, PCIe cannot establish a link, and ltssmstate changes between 2 and 3 several times, eventually staying at 2.Re: Stratix10 PCIe clock structure issue
Hi ventt, My reference clock comes from a crystal oscillator, which has a frequency of 100MHz , not the OSC-IN pin, OSC-IN connected to another 125MHz crystal oscillator. As shown in the figure, AV33,AV34,The common clock, connected to PC board via oculink. AT33, AT34 come from a crystal oscillator on FPGA board. AV33,AV34, This set of clocks is working normally. If I connect to AT33, AT34, Will not work properly and print errors. Please help investigating why the latter set of clocks is not working properly. Thanks.Stratix10 PCIe clock structure issue
Hello everyone， I am using quartus Pro 22.3 , device ( stratix10 1SX110HN2F43I2VG ) , IP core ( L-Tile and H-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express 22.2.0, GEN 3X4 125Mhz. ug_s10_pcie_avmm-683667-666643 shows that The Intel L-/H-Tile Avalon-MM for PCI Express IP supports the Separate Reference Clock With No Spread Spectrum architecture (SRNS), but not the Separate Reference Clock With Independent Spread Spectrum architecture (SRIS). When I use the Common Clock Architecture (pcie reference clock come from the PC board through the Oculink interface), everything is normal and the example design can run successfully. But when I modify the pin constraints and use a 100M local clock from the FPGA board, Linux kernel will continue to print errors and the example design cannot run normally. I don't think these clocks are spread spectrum clocks, what could be the possible reason for this ?
