Occasional Contributor
Frequent ContributorHi allen18,
Thank you for uploading the .ip file.
My apologies for the delayed response.
I have tested the Design Example generated from the .ip file you provided. I used a separate PCIe reference clock from a local source instead of the common clock method, and it successfully linked up at Gen3 x4 using Stratix 10 MX dev kit. In my environment, there is no option to enable Spread Spectrum Clocking (SSC) on the host, so I believe it is off as not supported.
Could you please share the .qsf file? Also, please ensure you follow the settings for using the separate clock architecture and meet the refclk requirements.
Thanks.
Best Regards,
Ven
Occasional ContributorHi ventt,
Thank you for your reply.
My qsf file is derived from the example design. Since the file was encrypted, I have copied its contents here. I believe there should not be significant differences between our QSF files.
Our current project can proceed using a common reference clock, so this issue does not affect the project timeline.
Your test results have proven that the example design can run normally on the development board, I suspect the problem might stem from either my current environment’s clock not meeting the reference clock requirements or potential PCB signal integrity issues. Could you provide the qar file for your current project? Then perhaps we can close this issue.
Thanks.
"""
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 22.3.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:13:13 NOVEMBER 07, 2024"
set_global_assignment -name LAST_QUARTUS_VERSION "22.3.0 Pro Edition"
set_global_assignment -name FAMILY "Stratix 10"
set_global_assignment -name DEVICE 1SX110HN2F43I2VG
set_global_assignment -name VERILOG_MACRO "ALTERA_EMIF_ENABLE_ISSP=1"
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4"
set_global_assignment -name USE_PWRMGT_SCL SDM_IO14
set_global_assignment -name USE_PWRMGT_SDA SDM_IO11
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 40
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name TOP_LEVEL_ENTITY pcie_ed
set_global_assignment -name IP_FILE ip/pcie_ed/pcie_ed_DUT.ip
set_global_assignment -name IP_FILE ip/pcie_ed/pcie_ed_resetIP.ip
set_global_assignment -name IP_FILE ip/pcie_ed/pcie_ed_MEM.ip
set_global_assignment -name QSYS_FILE pcie_ed.qsys
set_location_assignment PIN_AT34 -to refclk_clk
set_location_assignment PIN_AT33 -to "refclk_clk(n)"
set_location_assignment PIN_AW32 -to xcvr_rx_in3
set_location_assignment PIN_AW31 -to "xcvr_rx_in3(n)"
set_location_assignment PIN_BB30 -to xcvr_rx_in2
set_location_assignment PIN_BB29 -to "xcvr_rx_in2(n)"
set_location_assignment PIN_AY30 -to xcvr_rx_in1
set_location_assignment PIN_AY29 -to "xcvr_rx_in1(n)"
set_location_assignment PIN_AV30 -to xcvr_rx_in0
set_location_assignment PIN_AV29 -to "xcvr_rx_in0(n)"
set_location_assignment PIN_AY38 -to xcvr_tx_out3
set_location_assignment PIN_AY37 -to "xcvr_tx_out3(n)"
set_location_assignment PIN_BB38 -to xcvr_tx_out2
set_location_assignment PIN_BB37 -to "xcvr_tx_out2(n)"
set_location_assignment PIN_BA36 -to xcvr_tx_out1
set_location_assignment PIN_BA35 -to "xcvr_tx_out1(n)"
set_location_assignment PIN_BB34 -to xcvr_tx_out0
set_location_assignment PIN_BB33 -to "xcvr_tx_out0(n)"
set_instance_assignment -name IO_STANDARD LVDS -to refclk_clk -entity pcie_ed
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to xcvr_tx_out0 -entity pcie_ed
set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to xcvr_rx_in0 -entity pcie_ed
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to xcvr_tx_out1 -entity pcie_ed
set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to xcvr_rx_in1 -entity pcie_ed
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to xcvr_tx_out2 -entity pcie_ed
set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to xcvr_rx_in2 -entity pcie_ed
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to xcvr_tx_out3 -entity pcie_ed
set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to xcvr_rx_in3 -entity pcie_ed
set_location_assignment PIN_AC26 -to pcie_rstn_pin_perst
set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to pcie_rstn_pin_perst -entity pcie_ed
"""
