Isaac_V_Intel
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Re: AD9361 on Arrow SoC CV Kit , ERROR(CMD463) & ERROR(CMD656)
Hello Kaushal, I'm seeing that you are using an example developed in Xilinx, could you please follow our baremetal example for better support? Here is the link: https://rocketboards.org/foswiki/Documentation/SoCEDS#Cyclone_V_Bare_Metal_Example_Using_SoC_EDS_Standard_Edition Best regards, Isaac Vazquez.2KViews0likes0CommentsRe: run Eclipse get an error "wsl" not found in PATH"
Hello Mark, Did you follow the installation of the wsl package? if not, I'm going to leave the link of the WSL installation KDB. If the issue persist let me know! https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/tools/2019/how-do-i-install-the-windows--subsystem-for-linux---wsl--on-wind.html Best regards, Isaac Vazquez2.9KViews0likes1CommentRe: input pin to clock dff
Hello, There is no info in French, you can have information in Japanese, Chinese or English. You can find more info about clock management here: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyc3/cyc3_ciii51006.pdf Best regards.2.8KViews0likes1CommentRe: Quartus in Docker 18.0 standart uboot qeneration does not work
Hello, The version that you are using is 13.1, we did not support that version anymore, could you please refer to the next link, this is the updated version and follow all the steps please. https://rocketboards.org/foswiki/Documentation/BuildingBootloader Best regards, Isaac Vazquez.1.2KViews0likes0CommentsRe: A10SOC: "SPI FPGA IP"'s Interrupt Sender is "7", but in linux Device Tree "irqno" set to “26” ？Why
Hello. The "26" is because you have the interruption vector with 32 irq, also the irq have the 51 position. So, in the Linux case, you need to make the correct offset for the system understanding. Here is how the macro calculate the offset: #define BUTTON_PIO_IRQ (A10_HPS_BUTTON_PIO_IRQ + 51 - 32) Best regards, Isaac Vazquez.1.2KViews0likes1Comment