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Re: PCIe external DMA controller example
Hi Wincent Thank you very much for the detailed and patient explanation. it is very helpful. I can imagine there is a state machine to coordinate the information transfer back and forth. as a mid-level engineer, it is not trivial to figure out a state machine from scratch and verify it. my personal understanding is that Intel provides an example will be the easiest way for a develop like me. of course, Intel couldn't do everything for its developer. at least Intel keeps an approach for local DMA initialization. Again from the user guide, the purpose of the external DMA is listed very clearly. does Intel have an example of the following applications? Using the External DMA Descriptor Controller provides more flexibility. You can either modify or replace it to meet your system requirements.You may need to modify the DMA Descriptor Controller for the following reasons: • To implement multi-channel operation • To implement the descriptors as a linked list or to implement a custom DMA programming model • To store descriptors in a local memory, instead of system (host-side) memory To interface to the DMA logic included in this variant, the custom DMA descriptor controller must implement the following functions: • It must communicate with the Write Mover and Read Mover to copy the descriptor table to local memory. • The Write Mover and Read Mover must execute the descriptors stored in local memory. • The DMA Avalon-MM write (WrDCM_Master) and read (RdDCM_Master) masters must be able to update status to the TX slave (TXS). I hope there is a giant shoulder I can rely on, it not, it will be a good opportunity for me to enhance my develop experience. I will start from 5.1.7 appreciate your help. David2.4KViews0likes0CommentsRe: PCIe external DMA controller example
the example is using standard way to read descriptor from the host PC. I want to know how to read descriptor from other path like FPGA internal memory. • To store descriptors in a local memory, instead of system (host-side) memory. is it possible to get any detail document or instruction how to implement this feature. I attached QAR file which I created using the provided example. here is the instantiation of the module in the top. this is defined differently to the UG-01145_avmm_dma | 2021.06.03 I attached QAR file which I created using the provided example. here is the instantiation of the module in the top.2.4KViews0likes0CommentsPCIe external DMA controller example
Dear Intel Support/Expert I am building a PCIe DMA with external DMA descriptor controller. from user guide 10.2. Understanding the External DMA Descriptor Controller Using the External DMA Descriptor Controller provides more flexibility. You can either modify or replace it to meet your system requirements.You may need to modify the DMA Descriptor Controller for the following reasons: • To implement multi-channel operation • To implement the descriptors as a linked list or to implement a custom DMA programming model • To store descriptors in a local memory, instead of system (host-side) memory. is there a valid example to show how to store descriptors in a local memory? Thank you, DavidSolved2.6KViews0likes8CommentsRe: boardtestsystem not run
Hi Farabi, I installed a win7 and Quartus 18.1.0. now I can run boardtestsystem successfully. it is good news that my board and process is good, it is a good step forward. the bad news is that even on win7. I couldn't run Altera_pcie_gui. I have another thread in the forum. https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/detail-of-altera-pcie-gui-stop-run/m-p/1455189#M24087 please have a look if you are familiar with the PCie and program. Thank you very much. David2KViews0likes0Commentsdetail of altera_pcie_gui stop run
Dear Inter support. I have a PCIe project on A10, while I am not very confident that the platform is working. I decide to use the altera_pcie_gui to verify it. I downloaded the FPGA and driver, on win7. I believe I followed the instructions carefully, but the program still not working. I attached a file that describes my setup and execute procedure. hope someone who had run the program successfully before can give me some suggestions. thank you very much. David1.2KViews0likes4Commentslearning to load nios II program to A10 GX develop kit flash
Dear Intel Support and Expert While I am opening the Board Update Portal example with a 21.3 Quartus Pro. after I Open the IP for upgrade. I got the following error message. Info: Platform Designer Tip: Please Sync All System Infos before attempting to resolve the following error messages Error: a10_fpga_bup.sgdma_rx: Component altera_avalon_sgdma 15.1 not found or could not be instantiated Error: a10_fpga_bup.sgdma_tx: Component altera_avalon_sgdma 15.1 not found or could not be instantiated Error: a10_fpga_bup.sgdma_tx.m_read: Data width must be of power of two and between 8 and 4096 Error: a10_fpga_bup.sgdma_rx.m_write: Data width must be of power of two and between 8 and 4096 Error: a10_fpga_bup.sgdma_rx.descriptor_read: Data width must be of power of two and between 8 and 4096 Error: a10_fpga_bup.sgdma_tx.descriptor_read: Data width must be of power of two and between 8 and 4096 Error: a10_fpga_bup.sgdma_tx.descriptor_write: Data width must be of power of two and between 8 and 4096 Error: a10_fpga_bup.sgdma_rx.descriptor_write: Data width must be of power of two and between 8 and 4096 Error: a10_fpga_bup.sgdma_tx.csr: Data width must be of power of two and between 8 and 4096 Error: a10_fpga_bup.sgdma_rx.csr: Data width must be of power of two and between 8 and 4096 do I have to install a quartus version like 15.1? it is really painful to keep all the out of date Quartus version on my PC. I have learned how to build a Nios II project and load it through a cable to the FPGA, what I want to know is how to burn the Nios program .hex to A10 dev kit board flash. I am reading "edh_ed_handbook-683689-666980" chapter 5. I quote here: " The boot memory could be the Compact Flash Interface (CFI) flash, Intel MAX 10 User Flash Memory (UFM), Intel Serial Flash (EPCS)/Intel Quad Serial Flash (EPCQ) configuration device, Quad Serial Peripheral Interface (QSPI) flash or on-chip RAM (OCRAM). Regardless of the nature of the boot memory, HAL-based systems are constructed so that the reset vector and all program and data sections are initially stored in the boot memory. " what is the flash memory type on the A10 GX develop kit? I hope there is an example could show the procedure step and step clear and simple. to make my question clear, is there a tutorial to show the procedure to load NiosII .hex program to flash memory on the A10 Gx dev board and boot it successfully from there. Thank you, David803Views0likes4CommentsRe: Nios II example running on A10 GX dev kit.
Hi Kelly, 2)You could try the Board Update Portal Example Design which is to bring up an IP address on the board where this design consists of a NIOS II processor: https://www.intel.com/content/www/us/en/docs/programmable/683553/current/board-update-portal.html While I am open the example with a 21.3 Quartus Pro. after I Open the IP for upgrade. I got the following error message. Info: Platform Designer Tip: Please Sync All System Infos before attempting to resolve the following error messages Error: a10_fpga_bup.sgdma_rx: Component altera_avalon_sgdma 15.1 not found or could not be instantiated Error: a10_fpga_bup.sgdma_tx: Component altera_avalon_sgdma 15.1 not found or could not be instantiated Error: a10_fpga_bup.sgdma_tx.m_read: Data width must be of power of two and between 8 and 4096 Error: a10_fpga_bup.sgdma_rx.m_write: Data width must be of power of two and between 8 and 4096 Error: a10_fpga_bup.sgdma_rx.descriptor_read: Data width must be of power of two and between 8 and 4096 Error: a10_fpga_bup.sgdma_tx.descriptor_read: Data width must be of power of two and between 8 and 4096 Error: a10_fpga_bup.sgdma_tx.descriptor_write: Data width must be of power of two and between 8 and 4096 Error: a10_fpga_bup.sgdma_rx.descriptor_write: Data width must be of power of two and between 8 and 4096 Error: a10_fpga_bup.sgdma_tx.csr: Data width must be of power of two and between 8 and 4096 Error: a10_fpga_bup.sgdma_rx.csr: Data width must be of power of two and between 8 and 4096 do I have to install a quartus version like 15.1? it is really painful to keep all the history Quartus version on my PC. I have learned how to build a Nios II and load it through a cable to the FPGA, what I want to know is how to burn the Nios program to A10 dev kit board flash. I am reading "edh_ed_handbook-683689-666980" chapter 5. I hope there is an example could show the procedure clear and simple. to make my question clear, is there a tutorial to show the procedure to load NiosII program to flash and boot it successfully from there. Thank you, David1.8KViews0likes0Comments