ContributorPCIe external DMA controller example
Dear Intel Support/Expert
I am building a PCIe DMA with external DMA descriptor controller.
from user guide
- 10.2. Understanding the External DMA Descriptor Controller
Using the External DMA Descriptor Controller provides more flexibility. You can either
modify or replace it to meet your system requirements.You may need to modify the
DMA Descriptor Controller for the following reasons:
• To implement multi-channel operation
• To implement the descriptors as a linked list or to implement a custom DMA
programming model
• To store descriptors in a local memory, instead of system (host-side) memory.
is there a valid example to show how to store descriptors in a local memory?
Thank you,
David
Hi David,
EXPLANATION
The Descriptor Controller is essentially what controls the DMA transfers, and the CPU/control registers are used to interface with the descriptor controller. When an external descriptor controller is used, the use of the control registers becomes optional if you want to initiate locally. Our example design with external descriptor controller maintains the use of control registers as it assumes the host cpu controls the transfers -- but in reality, you have full control on when/how descriptors are sent to the read/write data movers.
In external descriptor controller "mode", avalon streaming interfaces are exposed, which is what you would use to feed the descriptors directly to the read/write data movers. In this mode, the implementation/storage of the descriptor table is up to the user, including when and how to send descriptors to the data movers. The requirement for you would be to send the descriptors in the correct format, and monitor the status buses (to see when tx/rx movers are ready to accept new data/done). You would then use the Txs interface to send status updates to the host.
Of course, this also assumes that your system is able to handle the system memory allocations accordingly and takes into account that the fpga is directly targeting system memory without communicating to the host aside from the 'completions'.
RECOMMENDATIONS
I would recommend going over Section 5 (IP Core Interfaces) of the IP user guide, and specifically Section 5.1.7 (Avalon-ST control interface for external descriptor controller) for details on the AVST interface. Section 10.2 also has details on using an external descriptor controller. Please download the User Guide as the online version is currently missing the core interface section (I will have this updated).
I also recommend reviewing our design example with the external descriptor controller, where you may inspect the example controller code and observe that the dma transfers are initiated by the controller itself (the controller reads the registers written by the host, but given host is bypassed, you can have your controller send descriptors to the dma ip directly based on your own criteria). You may find the example design ep_g3x8_avmm256.qsys, in the <quartus_install_dir>/ip/altera/altera_pcie/altera_pcie_a10_ed/example_design/a10 directory.
I know that was a lot of information! So please feel free to let me know if you need further clarifications.
Regards,
Wincent_Intel
