jackhab
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How to use DE10-nano HPS SPI on LTC connector
Hi I'm trying to bring-up Linux application which uses Cyclone V HPS SPI master connected to LTC connector on DE10-nano. After I couldn't get any live signal from SPI pins I tried the following. First I've found out that by default the SPI driver is connected to SPI master-0 which does not connected to anything on the board according the DE10-nano schematic. I recompiled Linux device tree to connect SPI driver to SPI master-1. I made sure I set the U2 mux pin IN to zero to select SPI connection. I still cannot get anything from SPI and I don't get any errors accessing SPI device from my application. Please, advice.991Views0likes3CommentsMAX10 Dual boot - is dual NIOS SW possible?
I'm starting with MAX10 RSU project and there is a image layout issue that is not clear to me. I need to have two FPGA designs: a factory design (capable of RSU) and a final application design. Each design also has its own NIOS SW. The on-chip flash IP has Initialize Flash Content Option set to OFF so that I will be able to add mem_init SW image later. In Convert Programming Files I create a POF from the two SOFs on page_0 and page_1. Now I want to attach each NIOS SW hex image to its corresponding FPGA design but Boot Info dialog only allows one hex file on UFM. Is it even possible to pack two different SW images for CFM0 and CFM1 SOFs or I can only have one SW image on UFM and it must be shared by both FPGA designs?Solved1.3KViews0likes4CommentsRe: Reading data from FPGA on HPS with Linux - what's the best way to do it?
Hi Tiwari I, indeed, use mmap() to gain access to FPGA memory space. But my question was about what happens during actual read and write. Should I read the memory word-by-word using alt_read_word() function or reading big memory chunks using standard memcpy() also OK? I am asking it because I'm not sure how ARM's data caching will behave during mempcpy() and I'm afraid caching can cause data corruption.2.1KViews0likes0CommentsReading data from FPGA on HPS with Linux - what's the best way to do it?
I have a Cyclone V with Linux application on ARM. The application accesses FPGA directly by mapping HW light- and heavy-weight bridges into virtual memory space (without kernel driver). Currently, I have a working application which does all access via alt_read_word() and alt_write_word(). I recall from NIOS documentation that this is the proper way to access HW memory to avoid caching issues but I couldn't find anything about it with regards to ARM. So I'd like to ask the following: Should FPGA memory be accessed by HPS only via SoCAL Memory Read/Write Utilities or it can be used as normal HPS RAM including calling memcopy() to move data between FPGA and HPS? Is there a document for SW developers which describes how HPS should access FPGA memory space? Thanks.2.2KViews0likes4CommentsRe: DE10-nano HPS boot from flash
Hi Aik, This is a bit strange because I when take the SD card out and set the MSEL switch to QSPI mode the board has FPGA configured after reset - the orange conf LED is on and user LEDs are blinking with a nice looking pattern. Probably, this Wiki page is not up to date. I suspect the problem is that Golden Reference design does not have QSPI as HPS peripheral.2.7KViews0likes0CommentsDE10-nano HPS boot from flash
Hello I was trying program bootloader to DE10-nano evaluation board and got the following error: $ quartus_hps.exe -c 1 -o PV 'c:\My\1609\preloader-mkpimage.bin' Current hardware is: DE-SoC [USB-1] Successfully change hardware frequency to 16Mhz Found HPS at device 1 Double check JTAG chain HPS Device IDCODE: 0x4BA00477 AHB Port is located at port 0 APB Port is located at port 1 Double check device identification ... Error: BSEL (5) is neither from NAND nor QSPI, set the correct BSEL and powercycle your board Error: Quartus Prime Programmer was unsuccessful. 0 errors, 0 warnings Error: Peak virtual memory: 4254 megabytes Error: Processing ended: Thu Aug 18 11:58:45 2022 Error: Elapsed time: 00:00:02 Error: Total CPU time (on all processors): 00:00:00 Later I found that Terasic DE10-nano Wiki says the board does not have neither NAND nor QSPI flash but the board schematic do shows S25FL128 flash connected to Cyclone V. When I set MSEL switch on board to EPCS configuration and I can see FPGA demo LEDs work so why can't I program this flash with HPS boot image? Thanks.2.7KViews0likes6CommentsBuilding FreeRTOS demo for Cyclone V fails
Hi I'm trying to build FreeRTOS demo (FreeRTOSv202112.00\FreeRTOS\Demo\CORTEX_A9_Cyclone_V_SoC_DK project) for Cyclone V using bare-metal compiler provided with Quartus 19.1. The build works until it reaches the alt_interrupt_armcc.s assembly file. At this points the assembler fails as if the file is in incompatible format: ../Altera_Code/HardwareLibrary/alt_interrupt_armcc.s: Assembler messages: ../Altera_Code/HardwareLibrary/alt_interrupt_armcc.s:1: Error: junk at end of line, first unrecognized character is `*' In the original Eclipse .cproject file the build tool location is C:\DevTools\altera\14.0\embedded\host_tools\mentor\gnu\arm\baremetal\bin This is a very old version of Altera SDK which is not even available for download, so I’m compiling with version 19.1 - its toolchain is in C:\intelFPGA\19.1\embedded\host_tools\mentor\gnu\arm\baremetal\bin. So I assume I’m using a newer version of the same compiler (as that used to create the demo) so it’s really strange the assembler fails to parse the file. It seems unlikely assembly format has changed between gcc version so what can cause such a problem? Is anyone aware of bare-metal RTOS (not necessarily FreeRTOS) examples which are known for sure to compile with the latest versions of either ARM Compiler or ARM gcc?1.8KViews0likes2Comments