MAX10 Dual boot - is dual NIOS SW possible?
I'm starting with MAX10 RSU project and there is a image layout issue that is not clear to me.
I need to have two FPGA designs: a factory design (capable of RSU) and a final application design. Each design also has its own NIOS SW.
The on-chip flash IP has Initialize Flash Content Option set to OFF so that I will be able to add mem_init SW image later.
In Convert Programming Files I create a POF from the two SOFs on page_0 and page_1.
Now I want to attach each NIOS SW hex image to its corresponding FPGA design but Boot Info dialog only allows one hex file on UFM.
Is it even possible to pack two different SW images for CFM0 and CFM1 SOFs or I can only have one SW image on UFM and it must be shared by both FPGA designs?
Hi,
Greetings and welcome to Intel's Forum.
Unfortunately, the UFM data (.HEX file) can be included in either Page_0 or Page_1 only. The On-chip flash does not support two .HEX files for Dual Compressed images configuration mode.
Here are additional information on the Max10 On Chip Flash for your reference:https://www.intel.com/content/www/us/en/docs/programmable/683689/current/fpga-on-chip-flash-description.html
Hope this clarify your doubts.
Thank you.
Kelly Jialin, GOH