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StefanG_Altera

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Joined 4 years ago

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Re: Cyclone V: how to boot Linux from QSPI?
Hi, The preloader should be placed at the beginning (0x0) of the QSPI address space. The "Building Bootloader for CV and A10" guide in RocketBoards provides an example on how OS (Linux), Preloader (4 x SPL and Full U-Boot) are prepared and flashed to QSPI via quartus_hps (chapter Cyclone V SoC - Boot from QSPI). https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10#Cyclone_V_SoC_45_Boot_from_QSPI See "C. QSPI Binaries" Hope this helps.
3 months ago Place SoC System
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Re: Agilex 5 GTS to HPS CDC/STA issue: help request!
Hi, Could you try "bridge disable" before "fpga load" at u-boot prompt? My understanding is that the configuration error reporting feature is incorporated in v25.1 embedded SW package (need to confirm). Could you try to compile your FPGA design (GHRD) with Quartus Pro 25.1 and build u-boot from our v25.1 fork? git clone -b QPDS25.1_REL_GSRD_PR https://github.com/altera-fpga/u-boot-socfpga As in the Agilex 5 Premium Development Kit Example in https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-5/e-series/premium/boot-examples/ug-linux-boot-agx5e-premium/#boot-from-sd-card You would need to include your defconfig (configs/socfpga_agilex5_atuma5_defconfig, include/configs/socfpga_agilex5_atuma5.h) and device trees in arch/arm/dts (socfpga_agilex5_atuma5.dts, socfpga_agilex5_atuma5-u-boot.dtsi). Regards, Stefan
4 months ago Place SoC System
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Re: Agilex 5 GTS to HPS CDC/STA issue: help request!
Hi, Ok I understand the "full test" image also failed to configure over JTAG but we lack more detailed information why. Can you please confirm the Quartus version you use? I assume you are using the HPs 1st mode configuration, please confirm. In this case can you stop at u-boot prompt and manually run fpga load, e.g. according to the u-boot bootcmd (CONFIG_BOOTCOMMAND environment example) in https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-5/e-series/modular/boot-examples/ug-linux-boot-agx5e-modular/#boot-from-sd-card CONFIG_BOOTCOMMAND="load mmc 0:1 \${loadaddr} ghrd.core.rbf; fpga load 0 \${loadaddr} \${filesize};bridge enable;.. In case of failure it should report an error code and related details, see an example capture below: Regards, Stefan
4 months ago Place SoC System
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Re: Agilex 5 GTS to HPS CDC/STA issue: help request!
Hi, Have you tried to configure the bitstream ("Full Test") via JTAG or at boot prompt (fpga load)? What Quartus Pro version and u-boot/linux branch versions are you using? Thanks. Regards, Stefan
4 months ago Place SoC System
2.6KViews
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Re: NIOS connected to IRQ from FPGA but not PIO
Hi, I am not sure why the BSP builder is not generating the right macro header values (system.h) for your custom component. Please try to use my component example as it worked on, my side. You may e.g. have some IRQ port interface settings not set right in your _hw.tcl file. Note: I used Quartus 22.1-std.
6 months ago Place Nios® System
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Re: Linux mSGDMA Driver Agilex 5
Hi, if you have a GHRD for your current board you can easily adapt the HW design (created for a supported board via e.g. build_hw_f2h_bridge.sh). The external periphery required on the demo designs is minimal (HPS-EMIF, HPS clock and UART).
6 months ago Place SoC System
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Re: NIOS handle IRQ from FPGA register
see answer on the new case (with same related issue) you opened: https://community.intel.com/t5/Nios-V-II-Embedded-Design-Suite/NIOS-connected-to-IRQ-from-FPGA-but-not-PIO/m-p/1693761/highlight/true#M53832:~:text=NIOS%20connected%20to%20IRQ%20from%20FPGA%20but%20not%20PIO
6 months ago Place Nios® System
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Re: NIOS connected to IRQ from FPGA but not PIO
Hi, as already mentioned on the previous case you created "NIOS handle IRQ from FPGA register": Your component is exposing 32 bits (as you show in the component editor window), try OR-ing them inside your IP RTL and modify to e.g. expose only one. The generated system.h file should reflect the IRQ line number and a non "-1" controller-ID, e.g.: #define BF5V_IRQ 4 #define BF5V_IRQ_INTERRUPT_CONTROLLER_ID 0 Your interrupt registration example code syntax looks correct to me. Below an example of a custom ip (timer) with a single IRQ out put that I tested on Nios II and works fine, it has only one IRQ. You can use as reference and modify to support more interrupts. The component files are in file ip.zip. - Instantiation of custom "timer" module: - system.h: /* * timer configuration * */ #define ALT_MODULE_CLASS_timer timer #define TIMER_BASE 0x81000 #define TIMER_IRQ 2 #define TIMER_IRQ_INTERRUPT_CONTROLLER_ID 0 #define TIMER_NAME "/dev/timer" #define TIMER_SPAN 16 #define TIMER_TYPE "timer" - example ot custom-timer interrupt implementation: .. #include "system.h" #include "sys/alt_irq.h" #include "Timer.h" alt_ic_isr_register (TIMER_IRQ_INTERRUPT_CONTROLLER_ID, TIMER_IRQ, timer_isr, (void*) dummy_ptr, 0); Timer_init (TIMER_BASE, // Initialize the timer component 50000000, // Write the reload value to the timer, 500ms Timer_Control_IRQ_EN // 0x04 : IRQ Enable | Timer_Control_AUTO_ACK); // 0x10 : Auto Acknowledge on Read
6 months ago Place Nios® System
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Re: Linux mSGDMA Driver Agilex 5
Hi, the agilex5-demo-hps2fpga-interfaces repo supports different boards including our Agilex 5 Premium Development kit (that features the device you mention). You can build the HW for one specific example (for one particular board) using the individual build scripts. First you have to initialize the HW build script for a particular board and build a specific HW project (e.g. build_hw_f2h_bridge.sh) as described in https://github.com/altera-fpga/agilex5-demo-hps2fpga-interfaces/blob/main/documentation/17_building_project.md In contrast to the board specific GHRD the demo designs are tailored for each test-case.
6 months ago Place SoC System
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Re: Linux mSGDMA Driver Agilex 5
Hi, You may be interested in checking the "HPS-FPGA Interface Demos" for Agilex 5. https://github.com/altera-fpga/agilex5-demo-hps2fpga-interfaces/blob/main/documentation/01_index.md The introductory documentation explains the demos repository concept and what examples are included. One example that may be of interest is the "F2H-Bridge": it uses a msgdma core to stream data across the F2H-Bridge from an internal FPGA RAM to EMIF buffer and vice-versa. Its a different approach than using a driver, the descriptors are pushed into the msgdma and the DMA duration time is computed in the app. https://github.com/altera-fpga/agilex5-demo-hps2fpga-interfaces/blob/main/documentation/10_menu_b_hw_f2h_bridge.md The demos are run under u-boot (using u-boot API) but some have been ported to Linux environment. The code of the "F2H-Bridge" Linux Application: https://github.com/altera-fpga/agilex5-demo-hps2fpga-interfaces/blob/main/common_sw/linux_apps/f2h_bridge.c
6 months ago Place SoC System
1.9KViews
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