NIOS connected to IRQ from FPGA but not PIO

Hi, as already mentioned on the previous case you created "NIOS handle IRQ from FPGA register":

Your component is exposing 32 bits (as you show in the component editor window), try OR-ing them inside your IP RTL and modify to e.g. expose only one.

The generated system.h file should reflect the IRQ line number and a non "-1" controller-ID, e.g.:
#define BF5V_IRQ 4
#define BF5V_IRQ_INTERRUPT_CONTROLLER_ID 0

Your interrupt registration example code syntax looks correct to me.

Below an example of a custom ip (timer) with a single IRQ out put that I tested on Nios II and works fine, it has only one IRQ. You can use as reference and modify to support more interrupts. The component files are in file ip.zip.

- Instantiation of custom "timer" module:

- system.h:

/*
* timer configuration
*
*/

#define ALT_MODULE_CLASS_timer timer
#define TIMER_BASE 0x81000
#define TIMER_IRQ 2
#define TIMER_IRQ_INTERRUPT_CONTROLLER_ID 0
#define TIMER_NAME "/dev/timer"
#define TIMER_SPAN 16
#define TIMER_TYPE "timer"

- example ot custom-timer interrupt implementation:

..

#include "system.h"
#include "sys/alt_irq.h"
#include "Timer.h"

alt_ic_isr_register (TIMER_IRQ_INTERRUPT_CONTROLLER_ID, TIMER_IRQ, timer_isr, (void*) dummy_ptr, 0);

Timer_init (TIMER_BASE, // Initialize the timer component
50000000, // Write the reload value to the timer, 500ms
Timer_Control_IRQ_EN // 0x04 : IRQ Enable
| Timer_Control_AUTO_ACK); // 0x10 : Auto Acknowledge on Read