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K606's avatar
K606
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4 months ago

Agilex 5 GTS to HPS CDC/STA issue: help request!

I am trying to bring-up the GTS component on the A5. The general idea is: Oscillator -> GTS -> FIFO -> DMA -> HPS -> Application. The Qsys diagram looks as followed (HPS section omitted for brevity...
Hps Boot
K606's avatar
K606
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4 months ago

It is Quartus 24.3. Yes it is in HPS First mode.

When executing the command you mentioned, I get this result: 

SOCFPGA_AGILEX5 # fpga load 0 ${fpgadata} ${fpgadatasize}
.............................................................FPGA reconfiguration failed!
Command 'load' failed: Error -110
StefanG_Altera's avatar
StefanG_Altera
Icon for Occasional Contributor rankOccasional Contributor
4 months ago

Hi,

Could you try "bridge disable" before "fpga load" at u-boot prompt?

My understanding is that the configuration error reporting feature is incorporated in v25.1 embedded SW package (need to confirm).

Could you try to compile your FPGA design (GHRD) with Quartus Pro 25.1 and build u-boot from our v25.1 fork?

git clone -b QPDS25.1_REL_GSRD_PR https://github.com/altera-fpga/u-boot-socfpga

As in the Agilex 5 Premium Development Kit Example in https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-5/e-series/premium/boot-examples/ug-linux-boot-agx5e-premium/#boot-from-sd-card

You would need to include your defconfig (configs/socfpga_agilex5_atuma5_defconfig, include/configs/socfpga_agilex5_atuma5.h) and device trees in arch/arm/dts (socfpga_agilex5_atuma5.dts, socfpga_agilex5_atuma5-u-boot.dtsi).

Regards,

Stefan

  • K606's avatar
    K606
    Icon for Contributor rankContributor
    4 months ago

    Hi

    I have discovered that replacing the line:

    .intel_directphy_gts_0_o_rx_parallel_data_o_rx_parallel_data     (gts_o_rx_parallel_data)

    with

    .intel_directphy_gts_0_o_rx_parallel_data_o_rx_parallel_data     (32'b0)

    Lets the system boot - based on this; what would you recommend?