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3f28dsboek

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Re: H-tile Hard IP for Ethernet Intel FPGA IP error
The error is because IP isn't correctly generated
3 years ago Place IP & Transceiver
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How to turn off FPGA when I don't need it?
How to turn off FPGA when I don't need it? Mine is straix 10 MX installed on a linux tower computer. Thank you!
Solved
3 years ago Place Boards & Dev Kits
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H-tile Hard IP for Ethernet Intel FPGA IP error
I generated a 100G H-tile Hard IP for Ethernet Intel FPGA IP, but when I compile the project it fails My device is Stratix 10 MX development board ( set_global_assignment -name DEVICE 1SM21BHU2F53E2VGS1) Can anyone help me? Thank you! Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 HSSI_CR2_PMA_RX_BUF(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (175001): The Fitter cannot place 1 HSSI_CR2_PMA_RX_BUF, which is within H-tile Hard IP for Ethernet Intel FPGA IP ex_100G_alt_ehipc2_1920_whg7r4i. Info (14596): Information about the failing component(s): Info (175028): The HSSI_CR2_PMA_RX_BUF name(s): av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|altera_xcvr_native_inst|g_native_phy_inst[1].s10_xcvr_native_inst|s10_xcvr_native_phy|g_xcvr_native_insts[0].ct2_xcvr_native_inst|inst_ct2_xcvr_channel_multi|gen_rev.ct2_xcvr_channel_inst|gen_ct1_hssi_cr2_pma_rx_buf.inst_ct1_hssi_cr2_pma_rx_buf Error (16234): No legal location could be found out of 96 considered location(s). Reasons why each location could not be used are summarized below: Error (175006): There is no routing connectivity between source HSSI_CR2_PMA_CDR_PLL and the HSSI_CR2_PMA_RX_BUF Info (175026): Source: HSSI_CR2_PMA_CDR_PLL av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|altera_xcvr_native_inst|g_native_phy_inst[1].s10_xcvr_native_inst|s10_xcvr_native_phy|g_xcvr_native_insts[0].ct2_xcvr_native_inst|inst_ct2_xcvr_channel_multi|gen_rev.ct2_xcvr_channel_inst|gen_ct1_hssi_cr2_pma_cdr_pll.inst_ct1_hssi_cr2_pma_cdr_pll Error (175022): The HSSI_CR2_PMA_CDR_PLL could not be placed in any location to satisfy its connectivity requirements Error (175022): The HSSI_CR2_PMA_RX_BUF could not be placed in any location to satisfy its connectivity requirements Info (175029): 96 locations affected Info (175029): HSSICR2PMARXBUF_1T1C0 Info (175029): HSSICR2PMARXBUF_1T1C1 Info (175029): HSSICR2PMARXBUF_1T1C2 Info (175029): HSSICR2PMARXBUF_1T1C3 Info (175029): HSSICR2PMARXBUF_1T1C4 Info (175029): HSSICR2PMARXBUF_1T1C5 Info (175029): HSSICR2PMARXBUF_1T1D0 Info (175029): HSSICR2PMARXBUF_1T1D1 Info (175029): HSSICR2PMARXBUF_1T1D2 Info (175029): HSSICR2PMARXBUF_1T1D3 Info (175029): HSSICR2PMARXBUF_1T1D4 Info (175029): HSSICR2PMARXBUF_1T1D5 Info (175029): and 84 more locations not displayed Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action. Error (16297): An error has occurred while trying to initialize the plan stage. Error: Quartus Prime Fitter was unsuccessful. 8 errors, 26 warnings Error: Peak virtual memory: 12571 megabytes Error: Processing ended: Mon Mar 21 01:36:04 2022 Error: Elapsed time: 00:02:09 Error: System process ID: 31615
Solved
3 years ago Place IP & Transceiver
860Views
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Re: IO stream
May I ask if I give up the OpenCL/DPC and turn to use RTL, should I use OPAE to take in UDP packets? If I understand correctly, UDP IP already is supported in the OPAE for PAC 5005, right? And we can't modify OpenCL or DPC BSP for PAC D5005, right? Will the situation change when OFS stack is rolled out?
3 years ago Place Acceleration
2.7KViews
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Re: IO stream
Can you also tell me which edition of bittware card supports oneAPI with UDP IP (simply ethernet IP) ? Thank you!
4 years ago Place Acceleration
2.8KViews
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Re: IO stream
Do you think it is possible for me to do DPC on an intel card with a modified BSP where I manually add an UDP IP using OPAE?
4 years ago Place Acceleration
2.8KViews
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IO stream
We noticed that there is an oneAPI FPGA example about io streaming based on D5005 https://github.com/oneapi-src/oneAPI-samples/tree/master/DirectProgramming/DPC%2B%2BFPGA/Tutorials/DesignPatterns/io_streaming But we found that D5005 BSP doesn't actually support UDP offload ip. Does there exist any board support truly IO streaming now ? ( not on fake data as shown in this example) Will D5005 BSP support IO streaming in the future? Is there any time estimation for IO streaming support? Thanks
Solved
4 years ago Place Acceleration
High-level Design Tools
2.8KViews
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9Comments
Is there any openCL example that uses above 70% DSP resource usage?
Does anyone know an example of an openCL fpga that uses 70%+ DSP resources? On stratix 10 is the best Or any RTL example that uses 70%+ DSP resources of stratix 10? Thanks a lot
Solved
4 years ago Place Quartus® Prime
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DSP can't routing
I am using openCL and the complier give the following error message Anyone can tell me how to analyze the error? In the report only DSP usage is above 25%, so the routing problem should due to DSP. Does that mean we can never make full use of DSP? What percentage of DSP is a reasonable design that can be routed? Thank you very much aoc device/matrix_mult.cl -o bin/matrix_mult.aocx -fp-relaxed -fpc -dont-error-if-large-area-est -no-interleaving=default --board pac_s10_dc Warning: Command has been deprecated. Please use -board=<value> instead of --board <value> aoc: Running OpenCL parser.... aoc: OpenCL parser completed successfully. aoc: Linking Object files.... aoc: Optimizing and doing static analysis of code... aoc: First stage compilation completed successfully. Compiling for FPGA. This process may take a long time, please be patient. Error (170143): Final fitting attempt was unsuccessful Error: An error occurred during routing Error: Quartus Prime Fitter was unsuccessful. 2 errors, 452 warnings Error (293001): Quartus Prime Full Compilation was unsuccessful. 3 errors, 2295 warnings Error (23035): Tcl error: ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last. Error (23031): Evaluation of Tcl script s10_partial_reconfig/flow.tcl unsuccessful Error: Quartus Prime Shell was unsuccessful. 9 errors, 2295 warnings Error (16546): Cannot load final database - ensure all earlier stages of the compiler have completed. Error (17941): The design could not be loaded due to errors. Error (23035): Tcl error: Error (23031): Evaluation of Tcl script scripts/adjust_plls_mcp.tcl unsuccessful Error: Quartus Prime Shell was unsuccessful. 4 errors, 0 warnings Error: Compiler Error, not able to generate hardware
Solved
4 years ago Place Acceleration
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Re: help for Error (170143): Final fitting attempt was unsuccessful
Hi Sheng, In the report only DSP usage is above 25%, so the routing problem should due to DSP. Does that mean we can never make full use of DSP? What percentage of DSP is a reasonable design that can be routed? Thank you very much
4 years ago Place Quartus® Prime
1.1KViews
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1Comment