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User1580871742356367
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JSED204B for Arria 10 SoC
I've implemented JESD204B receiver in Arria 10 SoC, 10AS066N2F40. I got it working in JMODE0/2 at sampling clock 1600MHz and 3200MHz. So the line rate is 6400Mbps and 12800Mbps and rxlink_clk is 160MHz and 320MHz respectively. The sysref to the FPGA is 10MHZ in both cases. However I could not get link-up, no device aligned nor device sync with sampling clock at 3125MHz in same JMODE. Where the line rate is 12500Mbps, rxlink_clk is 312.5MHz and sysref is 3.90625MHz. I did check the clocks etc. and they are fine. Any suggestions? Hope to hear from you ASAP. Thank you.PCIe
We have Arria 10 SOC (SX 066 NF40). There is PCIe hard IP at GXBL1D and GXBL1C. We like to implement a PCI4 Gen 3 with 4 lanes. #1 I like to check if any 4 lanes on these bank could be used? For example, two lanes from GXBL1D and two lanes from GXBL1C. #2 Was there any restriction for the REFCLK pin location? Hope to hear from ASAP. Thank you.NAND Flash Programming
#1 1. We use Arria 10 SoC 10AS066N2F40 with Micron MT29F1G08ABB NAND Flash. 2. We use or start with A10 GSRD and Arria 10 Flash Programming Alternative from RocketBoards.org to program the NAND (TFTP used). #2 We are experiencing about 15 to 20 minutes or so for programming entire NAND, or it's about 15 ms for a page. It seems slow. Was it the time required or reasonable? #3 I've tried to run a blank check with HPS_NAND_Programmer utility came with Quartus Prime Pro, yes, it took about 15 to 20 minutes to complete as well. #4 Why the programming time is so long? Thanks.io pin stuck
We are running into an issue with Arria 10 SoC FPGA (10AS066N2). We have two LED enable signals on pin J26 and D25 on bank 2K. It is the same bank that HPS DDR4 resides. 1. we have no problem to turn on and off both LED with FPGA only project(no HPS) 2. however we can only control one of the LED enabled from pin D25 with the project that has both HPS and FPGA. Any ideas. Thank you.
